perf vendor events power9: Fix commas so PMU event files are valid JSON (da3ef7f6) · Commits · 戴 / test

tools/perf/pmu-events/arch/powerpc/power9/cache.json

+22 −22

Original line number	Diff line number	Diff line
		[
		{,
		{
		"EventCode": "0x300F4",
		"EventName": "PM_THRD_CONC_RUN_INST",
		"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
		},
		{,
		{
		"EventCode": "0x1E056",
		"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
		"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
		},
		{,
		{
		"EventCode": "0x4D016",
		"EventName": "PM_CMPLU_STALL_FXLONG",
		"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
		},
		{,
		{
		"EventCode": "0x2D016",
		"EventName": "PM_CMPLU_STALL_FXU",
		"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
		},
		{,
		{
		"EventCode": "0x4D12A",
		"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
		"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
		},
		{,
		{
		"EventCode": "0x1003C",
		"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
		"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
		},
		{,
		{
		"EventCode": "0x4C014",
		"EventName": "PM_CMPLU_STALL_LMQ_FULL",
		"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
		},
		{,
		{
		"EventCode": "0x14048",
		"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
		"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
		},
		{,
		{
		"EventCode": "0x4D014",
		"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
		"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
		},
		{,
		{
		"EventCode": "0x2404A",
		"EventName": "PM_INST_FROM_RL4",
		"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
		},
		{,
		{
		"EventCode": "0x1404A",
		"EventName": "PM_INST_FROM_RL2L3_SHR",
		"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
		},
		{,
		{
		"EventCode": "0x401EA",
		"EventName": "PM_THRESH_EXC_128",
		"BriefDescription": "Threshold counter exceeded a value of 128"
		},
		{,
		{
		"EventCode": "0x400F6",
		"EventName": "PM_BR_MPRED_CMPL",
		"BriefDescription": "Number of Branch Mispredicts"
		},
		{,
		{
		"EventCode": "0x2F140",
		"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		{
		"EventCode": "0x101E6",
		"EventName": "PM_THRESH_EXC_4096",
		"BriefDescription": "Threshold counter exceed a count of 4096"
		},
		{,
		{
		"EventCode": "0x3F14A",
		"EventName": "PM_MRK_DPTEG_FROM_RMEM",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		{
		"EventCode": "0x4C016",
		"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
		"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
		},
		{,
		{
		"EventCode": "0x2C01A",
		"EventName": "PM_CMPLU_STALL_LHS",
		"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
		},
		{,
		{
		"EventCode": "0x401E4",
		"EventName": "PM_MRK_DTLB_MISS",
		"BriefDescription": "Marked dtlb miss"
		},
		{,
		{
		"EventCode": "0x24046",
		"EventName": "PM_INST_FROM_RL2L3_MOD",
		"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
		},
		{,
		{
		"EventCode": "0x1002A",
		"EventName": "PM_CMPLU_STALL_LARX",
		"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"

tools/perf/pmu-events/arch/powerpc/power9/floating-point.json

+7 −7

Original line number	Diff line number	Diff line
		[
		{,
		{
		"EventCode": "0x1415A",
		"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
		"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
		},
		{,
		{
		"EventCode": "0x10058",
		"EventName": "PM_MEM_LOC_THRESH_IFU",
		"BriefDescription": "Local Memory above threshold for IFU speculation control"
		},
		{,
		{
		"EventCode": "0x2D028",
		"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
		"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
		},
		{,
		{
		"EventCode": "0x30012",
		"EventName": "PM_FLUSH_COMPLETION",
		"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
		},
		{,
		{
		"EventCode": "0x2D154",
		"EventName": "PM_MRK_DERAT_MISS_64K",
		"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
		},
		{,
		{
		"EventCode": "0x4016E",
		"EventName": "PM_THRESH_NOT_MET",
		"BriefDescription": "Threshold counter did not meet threshold"

tools/perf/pmu-events/arch/powerpc/power9/frontend.json

+71 −71

Original line number	Diff line number	Diff line
		[
		{,
		{
		"EventCode": "0x25044",
		"EventName": "PM_IPTEG_FROM_L31_MOD",
		"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x101E8",
		"EventName": "PM_THRESH_EXC_256",
		"BriefDescription": "Threshold counter exceed a count of 256"
		},
		{,
		{
		"EventCode": "0x4504E",
		"EventName": "PM_IPTEG_FROM_L3MISS",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x1006A",
		"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
		"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it"
		},
		{,
		{
		"EventCode": "0x4E016",
		"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
		"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch"
		},
		{,
		{
		"EventCode": "0x1001A",
		"EventName": "PM_LSU_SRQ_FULL_CYC",
		"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource"
		},
		{,
		{
		"EventCode": "0x1E15E",
		"EventName": "PM_MRK_L2_TM_REQ_ABORT",
		"BriefDescription": "TM abort"
		},
		{,
		{
		"EventCode": "0x34052",
		"EventName": "PM_INST_SYS_PUMP_MPRED",
		"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch"
		},
		{,
		{
		"EventCode": "0x20114",
		"EventName": "PM_MRK_L2_RC_DISP",
		"BriefDescription": "Marked Instruction RC dispatched in L2"
		},
		{,
		{
		"EventCode": "0x4C044",
		"EventName": "PM_DATA_FROM_L31_ECO_MOD",
		"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load"
		},
		{,
		{
		"EventCode": "0x1C044",
		"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
		"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load"
		},
		{,
		{
		"EventCode": "0x44050",
		"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
		"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
		},
		{,
		{
		"EventCode": "0x30154",
		"EventName": "PM_MRK_FAB_RSP_DCLAIM",
		"BriefDescription": "Marked store had to do a dclaim"
		},
		{,
		{
		"EventCode": "0x30014",
		"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
		"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe"
		},
		{,
		{
		"EventCode": "0x3E054",
		"EventName": "PM_LD_MISS_L1",
		"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
		},
		{,
		{
		"EventCode": "0x2E01A",
		"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
		"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete"
		},
		{,
		{
		"EventCode": "0x2D01C",
		"EventName": "PM_CMPLU_STALL_STCX",
		"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2"
		},
		{,
		{
		"EventCode": "0x2C010",
		"EventName": "PM_CMPLU_STALL_LSU",
		"BriefDescription": "Completion stall by LSU instruction"
		},
		{,
		{
		"EventCode": "0x2C042",
		"EventName": "PM_DATA_FROM_L3_MEPF",
		"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load"
		},
		{,
		{
		"EventCode": "0x4E012",
		"EventName": "PM_CMPLU_STALL_MTFPSCR",
		"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)"
		},
		{,
		{
		"EventCode": "0x100F2",
		"EventName": "PM_1PLUS_PPC_CMPL",
		"BriefDescription": "1 or more ppc insts finished"
		},
		{,
		{
		"EventCode": "0x3001C",
		"EventName": "PM_LSU_REJECT_LMQ_FULL",
		"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)"
		},
		{,
		{
		"EventCode": "0x15046",
		"EventName": "PM_IPTEG_FROM_L31_SHR",
		"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x1015E",
		"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
		"BriefDescription": "Sampled Read got a T intervention"
		},
		{,
		{
		"EventCode": "0x101EC",
		"EventName": "PM_THRESH_MET",
		"BriefDescription": "threshold exceeded"
		},
		{,
		{
		"EventCode": "0x10020",
		"EventName": "PM_PMC4_REWIND",
		"BriefDescription": "PMC4 Rewind Event"
		},
		{,
		{
		"EventCode": "0x301EA",
		"EventName": "PM_THRESH_EXC_1024",
		"BriefDescription": "Threshold counter exceeded a value of 1024"
		},
		{,
		{
		"EventCode": "0x34056",
		"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
		"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned"
		},
		{,
		{
		"EventCode": "0x44056",
		"EventName": "PM_VECTOR_ST_CMPL",
		"BriefDescription": "Number of vector store instructions completed"
		},
		{,
		{
		"EventCode": "0x2C124",
		"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load"
		},
		{,
		{
		"EventCode": "0x4C12A",
		"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
		"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
		},
		{,
		{
		"EventCode": "0x30060",
		"EventName": "PM_TM_TRANS_RUN_INST",
		"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)"
		},
		{,
		{
		"EventCode": "0x2C014",
		"EventName": "PM_CMPLU_STALL_STORE_FINISH",
		"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish"
		},
		{,
		{
		"EventCode": "0x3515A",
		"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
		"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
		},
		{,
		{
		"EventCode": "0x34050",
		"EventName": "PM_INST_SYS_PUMP_CPRED",
		"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch"
		},
		{,
		{
		"EventCode": "0x3015E",
		"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
		"BriefDescription": "Sampled store did a rwitm and got a rty"
		},
		{,
		{
		"EventCode": "0x0",
		"EventName": "PM_SUSPENDED",
		"BriefDescription": "Counter OFF"
		},
		{,
		{
		"EventCode": "0x10010",
		"EventName": "PM_PMC4_OVERFLOW",
		"BriefDescription": "Overflow from counter 4"
		},
		{,
		{
		"EventCode": "0x3E04A",
		"EventName": "PM_DPTEG_FROM_RMEM",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		{
		"EventCode": "0x2F152",
		"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
		"BriefDescription": "cycles L2 RC took for a dclaim"
		},
		{,
		{
		"EventCode": "0x10004",
		"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
		"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others"
		},
		{,
		{
		"EventCode": "0x4F150",
		"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
		"BriefDescription": "cycles L2 RC took for a rwitm"
		},
		{,
		{
		"EventCode": "0x4E042",
		"EventName": "PM_DPTEG_FROM_L3",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		{
		"EventCode": "0x1F054",
		"EventName": "PM_TLB_HIT",
		"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT"
		},
		{,
		{
		"EventCode": "0x2C01E",
		"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
		"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt"
		},
		{,
		{
		"EventCode": "0x24050",
		"EventName": "PM_IOPS_CMPL",
		"BriefDescription": "Internal Operations completed"
		},
		{,
		{
		"EventCode": "0x1515C",
		"EventName": "PM_SYNC_MRK_BR_MPRED",
		"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt"
		},
		{,
		{
		"EventCode": "0x300FA",
		"EventName": "PM_INST_FROM_L3MISS",
		"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
		},
		{,
		{
		"EventCode": "0x15044",
		"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x15152",
		"EventName": "PM_SYNC_MRK_BR_LINK",
		"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt"
		},
		{,
		{
		"EventCode": "0x1E050",
		"EventName": "PM_CMPLU_STALL_TEND",
		"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2"
		},
		{,
		{
		"EventCode": "0x1013E",
		"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
		"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)"
		},
		{,
		{
		"EventCode": "0x25042",
		"EventName": "PM_IPTEG_FROM_L3_MEPF",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x14054",
		"EventName": "PM_INST_PUMP_CPRED",
		"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch"
		},
		{,
		{
		"EventCode": "0x4015E",
		"EventName": "PM_MRK_FAB_RSP_RD_RTY",
		"BriefDescription": "Sampled L2 reads retry count"
		},
		{,
		{
		"EventCode": "0x45048",
		"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
		"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x44052",
		"EventName": "PM_INST_PUMP_MPRED",
		"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch"
		},
		{,
		{
		"EventCode": "0x30026",
		"EventName": "PM_CMPLU_STALL_STORE_DATA",
		"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data"
		},
		{,
		{
		"EventCode": "0x301E6",
		"EventName": "PM_MRK_DERAT_MISS",
		"BriefDescription": "Erat Miss (TLB Access) All page sizes"
		},
		{,
		{
		"EventCode": "0x24154",
		"EventName": "PM_THRESH_ACC",
		"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs."
		},
		{,
		{
		"EventCode": "0x2015E",
		"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
		"BriefDescription": "Sampled store did a rwitm and got a rty"
		},
		{,
		{
		"EventCode": "0x200FA",
		"EventName": "PM_BR_TAKEN_CMPL",
		"BriefDescription": "New event for Branch Taken"
		},
		{,
		{
		"EventCode": "0x35044",
		"EventName": "PM_IPTEG_FROM_L31_ECO_SHR",
		"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request"
		},
		{,
		{
		"EventCode": "0x4C010",
		"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
		"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration"
		},
		{,
		{
		"EventCode": "0x4C01C",
		"EventName": "PM_CMPLU_STALL_ST_FWD",
		"BriefDescription": "Completion stall due to store forward"
		},
		{,
		{
		"EventCode": "0x3515C",
		"EventName": "PM_MRK_DATA_FROM_RL4",
		"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
		},
		{,
		{
		"EventCode": "0x2D14C",
		"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR",
		"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
		},
		{,
		{
		"EventCode": "0x40116",
		"EventName": "PM_MRK_LARX_FIN",
		"BriefDescription": "Larx finished"
		},
		{,
		{
		"EventCode": "0x1003A",
		"EventName": "PM_CMPLU_STALL_LSU_FIN",
		"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish"
		},
		{,
		{
		"EventCode": "0x3012A",
		"EventName": "PM_MRK_L2_RC_DONE",
		"BriefDescription": "Marked RC done"
		},
		{,
		{
		"EventCode": "0x45044",
		"EventName": "PM_IPTEG_FROM_L31_ECO_MOD",
		"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"

tools/perf/pmu-events/arch/powerpc/power9/marked.json

+125 −125

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/powerpc/power9/memory.json

+26 −26

File changed.

Preview size limit exceeded, changes collapsed.

Admin message