Unverified Commit da3e83f8 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Mark Brown
Browse files

ASoC: wcd934x: add audio routings 



This patch adds audio routing for both playback and capture.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20191219103153.14875-8-srinivas.kandagatla@linaro.org


Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a70d9245

sound/soc/codecs/wcd934x.c

+290 −0
Original line number Diff line number Diff line
@@ -135,6 +135,162 @@ 
	} \

}



#define WCD934X_INTERPOLATOR_PATH(id)			\

	{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},	\

	{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},	\

	{"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},	\

	{"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},	\

	{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},	\

	{"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},	\

	{"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},	\

	{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},	\

	{"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},		\

	{"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},		\

	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \

	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \

	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \

	{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},	\

	{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},	\

	{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},	\

	{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},	\

	{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},	\

	{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},	\

	{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},	\

	{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},	\

	{"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \

	{"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \

	{"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},	\

	{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},	\

	{"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},	\

	{"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},	\

	{"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},	\

	{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}



#define WCD934X_INTERPOLATOR_MIX2(id)			\

	{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \

	{"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}



#define WCD934X_SLIM_RX_AIF_PATH(id)	\

	{"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},	\

	{"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},	\

	{"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},	\

	{"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \

	{"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}



#define WCD934X_ADC_MUX(id) \

	{"ADC MUX" #id, "DMIC", "DMIC MUX" #id },	\

	{"ADC MUX" #id, "AMIC", "AMIC MUX" #id },	\

	{"DMIC MUX" #id, "DMIC0", "DMIC0"},		\

	{"DMIC MUX" #id, "DMIC1", "DMIC1"},		\

	{"DMIC MUX" #id, "DMIC2", "DMIC2"},		\

	{"DMIC MUX" #id, "DMIC3", "DMIC3"},		\

	{"DMIC MUX" #id, "DMIC4", "DMIC4"},		\

	{"DMIC MUX" #id, "DMIC5", "DMIC5"},		\

	{"AMIC MUX" #id, "ADC1", "ADC1"},		\

	{"AMIC MUX" #id, "ADC2", "ADC2"},		\

	{"AMIC MUX" #id, "ADC3", "ADC3"},		\

	{"AMIC MUX" #id, "ADC4", "ADC4"}



#define WCD934X_IIR_INP_MUX(id) \

	{"IIR" #id, NULL, "IIR" #id " INP0 MUX"},	\

	{"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},	\

	{"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},	\

	{"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},	\

	{"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},	\

	{"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},	\

	{"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},	\

	{"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},	\

	{"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},	\

	{"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},	\

	{"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},	\

	{"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},	\

	{"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},	\

	{"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},	\

	{"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},	\

	{"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},	\

	{"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},	\

	{"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},	\

	{"IIR" #id, NULL, "IIR" #id " INP1 MUX"},	\

	{"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},	\

	{"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},	\

	{"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},	\

	{"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},	\

	{"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},	\

	{"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},	\

	{"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},	\

	{"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},	\

	{"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},	\

	{"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},	\

	{"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},	\

	{"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},	\

	{"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},	\

	{"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},	\

	{"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},	\

	{"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},	\

	{"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},	\

	{"IIR" #id, NULL, "IIR" #id " INP2 MUX"},	\

	{"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},	\

	{"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},	\

	{"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},	\

	{"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},	\

	{"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},	\

	{"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},	\

	{"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},	\

	{"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},	\

	{"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},	\

	{"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},	\

	{"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},	\

	{"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},	\

	{"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},	\

	{"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},	\

	{"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},	\

	{"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},	\

	{"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},	\

	{"IIR" #id, NULL, "IIR" #id " INP3 MUX"},	\

	{"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},	\

	{"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},	\

	{"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},	\

	{"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},	\

	{"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},	\

	{"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},	\

	{"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},	\

	{"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},	\

	{"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},	\

	{"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},	\

	{"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},	\

	{"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},	\

	{"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},	\

	{"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},	\

	{"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},	\

	{"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},	\

	{"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}



#define WCD934X_SLIM_TX_AIF_PATH(id)	\

	{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\

	{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\

	{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\

	{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}



enum {

	MIC_BIAS_1 = 1,

	MIC_BIAS_2,
@@ -4678,6 +4834,138 @@ static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 
			   ARRAY_SIZE(aif3_slim_cap_mixer)),

};



static const struct snd_soc_dapm_route wcd934x_audio_map[] = {

	/* RX0-RX7 */

	WCD934X_SLIM_RX_AIF_PATH(0),

	WCD934X_SLIM_RX_AIF_PATH(1),

	WCD934X_SLIM_RX_AIF_PATH(2),

	WCD934X_SLIM_RX_AIF_PATH(3),

	WCD934X_SLIM_RX_AIF_PATH(4),

	WCD934X_SLIM_RX_AIF_PATH(5),

	WCD934X_SLIM_RX_AIF_PATH(6),

	WCD934X_SLIM_RX_AIF_PATH(7),



	/* RX0 Ear out */

	WCD934X_INTERPOLATOR_PATH(0),

	WCD934X_INTERPOLATOR_MIX2(0),

	{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},

	{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},

	{"RX INT0 DAC", NULL, "RX_BIAS"},

	{"EAR PA", NULL, "RX INT0 DAC"},

	{"EAR", NULL, "EAR PA"},



	/* RX1 Headphone left */

	WCD934X_INTERPOLATOR_PATH(1),

	WCD934X_INTERPOLATOR_MIX2(1),

	{"RX INT1 MIX3", NULL, "RX INT1 MIX2"},

	{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},

	{"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},

	{"RX INT1 DAC", NULL, "RX_BIAS"},

	{"HPHL PA", NULL, "RX INT1 DAC"},

	{"HPHL", NULL, "HPHL PA"},



	/* RX2 Headphone right */

	WCD934X_INTERPOLATOR_PATH(2),

	WCD934X_INTERPOLATOR_MIX2(2),

	{"RX INT2 MIX3", NULL, "RX INT2 MIX2"},

	{"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},

	{"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},

	{"RX INT2 DAC", NULL, "RX_BIAS"},

	{"HPHR PA", NULL, "RX INT2 DAC"},

	{"HPHR", NULL, "HPHR PA"},



	/* RX3 HIFi LineOut1 */

	WCD934X_INTERPOLATOR_PATH(3),

	WCD934X_INTERPOLATOR_MIX2(3),

	{"RX INT3 MIX3", NULL, "RX INT3 MIX2"},

	{"RX INT3 DAC", NULL, "RX INT3 MIX3"},

	{"RX INT3 DAC", NULL, "RX_BIAS"},

	{"LINEOUT1 PA", NULL, "RX INT3 DAC"},

	{"LINEOUT1", NULL, "LINEOUT1 PA"},



	/* RX4 HIFi LineOut2 */

	WCD934X_INTERPOLATOR_PATH(4),

	WCD934X_INTERPOLATOR_MIX2(4),

	{"RX INT4 MIX3", NULL, "RX INT4 MIX2"},

	{"RX INT4 DAC", NULL, "RX INT4 MIX3"},

	{"RX INT4 DAC", NULL, "RX_BIAS"},

	{"LINEOUT2 PA", NULL, "RX INT4 DAC"},

	{"LINEOUT2", NULL, "LINEOUT2 PA"},



	/* RX7 Speaker Left Out PA */

	WCD934X_INTERPOLATOR_PATH(7),

	WCD934X_INTERPOLATOR_MIX2(7),

	{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},

	{"RX INT7 CHAIN", NULL, "RX_BIAS"},

	{"RX INT7 CHAIN", NULL, "SBOOST0"},

	{"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},

	{"SPK1 OUT", NULL, "RX INT7 CHAIN"},



	/* RX8 Speaker Right Out PA */

	WCD934X_INTERPOLATOR_PATH(8),

	{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},

	{"RX INT8 CHAIN", NULL, "RX_BIAS"},

	{"RX INT8 CHAIN", NULL, "SBOOST1"},

	{"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},

	{"SPK2 OUT", NULL, "RX INT8 CHAIN"},



	/* Tx */

	{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},

	{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},

	{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},



	WCD934X_SLIM_TX_AIF_PATH(0),

	WCD934X_SLIM_TX_AIF_PATH(1),

	WCD934X_SLIM_TX_AIF_PATH(2),

	WCD934X_SLIM_TX_AIF_PATH(3),

	WCD934X_SLIM_TX_AIF_PATH(4),

	WCD934X_SLIM_TX_AIF_PATH(5),

	WCD934X_SLIM_TX_AIF_PATH(6),

	WCD934X_SLIM_TX_AIF_PATH(7),

	WCD934X_SLIM_TX_AIF_PATH(8),



	WCD934X_ADC_MUX(0),

	WCD934X_ADC_MUX(1),

	WCD934X_ADC_MUX(2),

	WCD934X_ADC_MUX(3),

	WCD934X_ADC_MUX(4),

	WCD934X_ADC_MUX(5),

	WCD934X_ADC_MUX(6),

	WCD934X_ADC_MUX(7),

	WCD934X_ADC_MUX(8),



	{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},

	{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},

	{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},

	{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},

	{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},

	{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},

	{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},

	{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},

	{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},



	{"AMIC4_5 SEL", "AMIC4", "AMIC4"},

	{"AMIC4_5 SEL", "AMIC5", "AMIC5"},



	{ "DMIC0", NULL, "DMIC0 Pin" },

	{ "DMIC1", NULL, "DMIC1 Pin" },

	{ "DMIC2", NULL, "DMIC2 Pin" },

	{ "DMIC3", NULL, "DMIC3 Pin" },

	{ "DMIC4", NULL, "DMIC4 Pin" },

	{ "DMIC5", NULL, "DMIC5 Pin" },



	{"ADC1", NULL, "AMIC1"},

	{"ADC2", NULL, "AMIC2"},

	{"ADC3", NULL, "AMIC3"},

	{"ADC4", NULL, "AMIC4_5 SEL"},



	WCD934X_IIR_INP_MUX(0),

	WCD934X_IIR_INP_MUX(1),



	{"SRC0", NULL, "IIR0"},

	{"SRC1", NULL, "IIR1"},

};



static const struct snd_soc_component_driver wcd934x_component_drv = {

	.probe = wcd934x_comp_probe,

	.remove = wcd934x_comp_remove,
@@ -4686,6 +4974,8 @@ static const struct snd_soc_component_driver wcd934x_component_drv = { 
	.num_controls = ARRAY_SIZE(wcd934x_snd_controls),

	.dapm_widgets = wcd934x_dapm_widgets,

	.num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),

	.dapm_routes = wcd934x_audio_map,

	.num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),

};



static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)

CRA Git | Maintained and supported by SUSTech CRA and CCSE