Commit da32cc90 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2013-11-29' of... 

Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

- some more ppgtt prep patches from Ben
- a few fbc fixes from Ville
- power well rework from Imre
- vlv forcewake improvements from Deepak S, Ville and Jesse
- a few smaller things all over

[airlied: fixup forwcewake conflict]
* tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel: (97 commits)
  drm/i915: Fix port name in vlv_wait_port_ready() timeout warning
  drm/i915: Return a drm_mode_status enum in the mode_valid vfuncs
  drm/i915: add intel_display_power_enabled_sw() for use in atomic ctx
  drm/i915: drop DRM_ERROR in intel_fbdev init
  drm/i915/vlv: use parallel context restore when coming out of RC6
  drm/i915/vlv: use a lower RC6 timeout on VLV
  drm/i915/sdvo: Fix up debug output to not split lines
  drm/i915: make sparse happy for the new vlv mmio read function
  drm/i915: drop the right force-wake engine in the vlv mmio funcs
  drm/i915: Fix GT wake FIFO free entries for VLV
  drm/i915: Report all GTFIFODBG errors
  drm/i915: Enabling DebugFS for valleyview forcewake counts
  drm/i915/vlv: Valleyview support for forcewake Individual power wells.
  drm/i915: Add power well arguments to force wake routines.
  drm/i915: Do not attempt to re-enable an unconnected primary plane
  drm/i915: add a debugfs entry for power domain info
  drm/i915: add a default always-on power well
  drm/i915: don't do BDW/HSW specific powerdomains init on other platforms
  drm/i915: protect HSW power well check with IS_HASWELL in redisable_vga
  drm/i915: use IS_HASWELL/BROADWELL instead of HAS_POWER_WELL
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
parents 319e2e3f be46ffd4

drivers/char/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ obj-$(CONFIG_GPIO_TB0219) += tb0219.o 
obj-$(CONFIG_TELCLOCK)		+= tlclk.o



obj-$(CONFIG_MWAVE)		+= mwave/

obj-$(CONFIG_AGP)		+= agp/

obj-y				+= agp/

obj-$(CONFIG_PCMCIA)		+= pcmcia/



obj-$(CONFIG_HANGCHECK_TIMER)	+= hangcheck-timer.o

drivers/char/agp/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ config AGP_AMD64 
config AGP_INTEL

	tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support"

	depends on AGP && X86

	select INTEL_GTT

	help

	  This option gives you AGP support for the GLX component of X

	  on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875,
@@ -155,3 +156,7 @@ config AGP_SGI_TIOCA 
          This option gives you AGP GART support for the SGI TIO chipset

          for IA64 processors.



config INTEL_GTT

	tristate

	depends on X86 && PCI

drivers/char/agp/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o 
obj-$(CONFIG_AGP_PARISC)	+= parisc-agp.o

obj-$(CONFIG_AGP_I460)		+= i460-agp.o

obj-$(CONFIG_AGP_INTEL)		+= intel-agp.o

obj-$(CONFIG_AGP_INTEL)		+= intel-gtt.o

obj-$(CONFIG_INTEL_GTT)		+= intel-gtt.o

obj-$(CONFIG_AGP_NVIDIA)	+= nvidia-agp.o

obj-$(CONFIG_AGP_SGI_TIOCA)	+= sgi-agp.o

obj-$(CONFIG_AGP_SIS)		+= sis-agp.o

drivers/char/agp/intel-agp.c

+0 −5
Original line number Diff line number Diff line
@@ -14,9 +14,6 @@ 
#include "intel-agp.h"

#include <drm/intel-gtt.h>



int intel_agp_enabled;

EXPORT_SYMBOL(intel_agp_enabled);



static int intel_fetch_size(void)

{

	int i;
@@ -814,8 +811,6 @@ static int agp_intel_probe(struct pci_dev *pdev, 
found_gmch:

	pci_set_drvdata(pdev, bridge);

	err = agp_add_bridge(bridge);

	if (!err)

		intel_agp_enabled = 1;

	return err;

}

drivers/char/agp/intel-gtt.c

+18 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static struct _intel_private { 
#define IS_IRONLAKE	intel_private.driver->is_ironlake

#define HAS_PGTBL_EN	intel_private.driver->has_pgtbl_enable



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int intel_gtt_map_memory(struct page **pages,

				unsigned int num_entries,

				struct sg_table *st)
@@ -168,6 +169,7 @@ static void i8xx_destroy_pages(struct page *page) 
	__free_pages(page, 2);

	atomic_dec(&agp_bridge->current_memory_agp);

}

#endif



#define I810_GTT_ORDER 4

static int i810_setup(void)
@@ -209,6 +211,7 @@ static void i810_cleanup(void) 
	free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);

}



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,

				      int type)

{
@@ -289,6 +292,7 @@ static void intel_i810_free_by_type(struct agp_memory *curr) 
	}

	kfree(curr);

}

#endif



static int intel_gtt_setup_scratch_page(void)

{
@@ -647,7 +651,9 @@ static int intel_gtt_init(void) 
		return -ENOMEM;

	}



#if IS_ENABLED(CONFIG_AGP_INTEL)

	global_cache_flush();   /* FIXME: ? */

#endif



	intel_private.stolen_size = intel_gtt_stolen_size();
@@ -671,6 +677,7 @@ static int intel_gtt_init(void) 
	return 0;

}



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int intel_fake_agp_fetch_size(void)

{

	int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
@@ -689,6 +696,7 @@ static int intel_fake_agp_fetch_size(void) 


	return 0;

}

#endif



static void i830_cleanup(void)

{
@@ -801,6 +809,7 @@ static int i830_setup(void) 
	return 0;

}



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)

{

	agp_bridge->gatt_table_real = NULL;
@@ -825,6 +834,7 @@ static int intel_fake_agp_configure(void) 


	return 0;

}

#endif



static bool i830_check_flags(unsigned int flags)

{
@@ -863,6 +873,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, 
}

EXPORT_SYMBOL(intel_gtt_insert_sg_entries);



#if IS_ENABLED(CONFIG_AGP_INTEL)

static void intel_gtt_insert_pages(unsigned int first_entry,

				   unsigned int num_entries,

				   struct page **pages,
@@ -928,6 +939,7 @@ out_err: 
	mem->is_flushed = true;

	return ret;

}

#endif



void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)

{
@@ -941,6 +953,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 
}

EXPORT_SYMBOL(intel_gtt_clear_range);



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int intel_fake_agp_remove_entries(struct agp_memory *mem,

					 off_t pg_start, int type)

{
@@ -982,6 +995,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 
	/* always return NULL for other allocation types for now */

	return NULL;

}

#endif



static int intel_alloc_chipset_flush_resource(void)

{
@@ -1138,6 +1152,7 @@ static int i9xx_setup(void) 
	return 0;

}



#if IS_ENABLED(CONFIG_AGP_INTEL)

static const struct agp_bridge_driver intel_fake_agp_driver = {

	.owner			= THIS_MODULE,

	.size_type		= FIXED_APER_SIZE,
@@ -1159,6 +1174,7 @@ static const struct agp_bridge_driver intel_fake_agp_driver = { 
	.agp_destroy_page	= agp_generic_destroy_page,

	.agp_destroy_pages      = agp_generic_destroy_pages,

};

#endif



static const struct intel_gtt_driver i81x_gtt_driver = {

	.gen = 1,
@@ -1376,11 +1392,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 


	intel_private.refcount++;



#if IS_ENABLED(CONFIG_AGP_INTEL)

	if (bridge) {

		bridge->driver = &intel_fake_agp_driver;

		bridge->dev_private_data = &intel_private;

		bridge->dev = bridge_pdev;

	}

#endif



	intel_private.bridge_dev = pci_dev_get(bridge_pdev);

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