Commit da16349d authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-dsa-Global-2-cosmetics' 



Vivien Didelot says:

====================
net: dsa: Global 2 cosmetics

Similarly to what has been done for the Port and Global 1 registers,
this patch series prefixes and documents the macros of Global 2.

It brings no functional changes except for 1/10 which fixes the IRL init
for 88E6390 family.

Changes in v2: make *_g2_irl_init_all static inline without
NET_DSA_MV88E6XXX_GLOBAL2 and compile test with and without the symbol.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents cc07cb93 1d90016d

drivers/net/dsa/mv88e6xxx/chip.c

+47 −0
Original line number Diff line number Diff line
@@ -941,6 +941,26 @@ static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);

}



static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)

{

	int port;

	int err;



	if (!chip->info->ops->irl_init_all)

		return 0;



	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {

		/* Disable ingress rate limiting by resetting all per port

		 * ingress rate limit resources to their initial state.

		 */

		err = chip->info->ops->irl_init_all(chip, port);

		if (err)

			return err;

	}



	return 0;

}



static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)

{

	u16 pvlan = 0;
@@ -2102,6 +2122,10 @@ static int mv88e6xxx_setup(struct dsa_switch *ds) 
			goto unlock;

	}



	err = mv88e6xxx_irl_setup(chip);

	if (err)

		goto unlock;



	err = mv88e6xxx_phy_setup(chip);

	if (err)

		goto unlock;
@@ -2339,6 +2363,7 @@ static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 


static const struct mv88e6xxx_ops mv88e6085_ops = {

	/* MV88E6XXX_FAMILY_6097 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,

	.phy_read = mv88e6185_phy_ppu_read,

	.phy_write = mv88e6185_phy_ppu_write,
@@ -2393,6 +2418,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { 


static const struct mv88e6xxx_ops mv88e6097_ops = {

	/* MV88E6XXX_FAMILY_6097 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -2423,6 +2449,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { 


static const struct mv88e6xxx_ops mv88e6123_ops = {

	/* MV88E6XXX_FAMILY_6165 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -2479,6 +2506,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { 


static const struct mv88e6xxx_ops mv88e6141_ops = {

	/* MV88E6XXX_FAMILY_6341 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2512,6 +2540,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = { 


static const struct mv88e6xxx_ops mv88e6161_ops = {

	/* MV88E6XXX_FAMILY_6165 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -2542,6 +2571,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { 


static const struct mv88e6xxx_ops mv88e6165_ops = {

	/* MV88E6XXX_FAMILY_6165 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6165_phy_read,

	.phy_write = mv88e6165_phy_write,
@@ -2565,6 +2595,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = { 


static const struct mv88e6xxx_ops mv88e6171_ops = {

	/* MV88E6XXX_FAMILY_6351 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -2596,6 +2627,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { 


static const struct mv88e6xxx_ops mv88e6172_ops = {

	/* MV88E6XXX_FAMILY_6352 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2630,6 +2662,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { 


static const struct mv88e6xxx_ops mv88e6175_ops = {

	/* MV88E6XXX_FAMILY_6351 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -2661,6 +2694,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { 


static const struct mv88e6xxx_ops mv88e6176_ops = {

	/* MV88E6XXX_FAMILY_6352 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2722,6 +2756,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { 


static const struct mv88e6xxx_ops mv88e6190_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2755,6 +2790,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { 


static const struct mv88e6xxx_ops mv88e6190x_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2788,6 +2824,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { 


static const struct mv88e6xxx_ops mv88e6191_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2821,6 +2858,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { 


static const struct mv88e6xxx_ops mv88e6240_ops = {

	/* MV88E6XXX_FAMILY_6352 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2855,6 +2893,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { 


static const struct mv88e6xxx_ops mv88e6290_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2889,6 +2928,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 


static const struct mv88e6xxx_ops mv88e6320_ops = {

	/* MV88E6XXX_FAMILY_6320 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2920,6 +2960,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 


static const struct mv88e6xxx_ops mv88e6321_ops = {

	/* MV88E6XXX_FAMILY_6321 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2950,6 +2991,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 


static const struct mv88e6xxx_ops mv88e6341_ops = {

	/* MV88E6XXX_FAMILY_6341 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -2983,6 +3025,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = { 


static const struct mv88e6xxx_ops mv88e6350_ops = {

	/* MV88E6XXX_FAMILY_6351 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -3014,6 +3057,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { 


static const struct mv88e6xxx_ops mv88e6351_ops = {

	/* MV88E6XXX_FAMILY_6351 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,
@@ -3045,6 +3089,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { 


static const struct mv88e6xxx_ops mv88e6352_ops = {

	/* MV88E6XXX_FAMILY_6352 */

	.irl_init_all = mv88e6352_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom16,

	.set_eeprom = mv88e6xxx_g2_set_eeprom16,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -3079,6 +3124,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { 


static const struct mv88e6xxx_ops mv88e6390_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -3115,6 +3161,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { 


static const struct mv88e6xxx_ops mv88e6390x_ops = {

	/* MV88E6XXX_FAMILY_6390 */

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

drivers/net/dsa/mv88e6xxx/chip.h

+3 −16
Original line number Diff line number Diff line
@@ -121,8 +121,6 @@ enum mv88e6xxx_cap { 
	MV88E6XXX_CAP_G2_INT,		/* (0x00) Interrupt Status */

	MV88E6XXX_CAP_G2_MGMT_EN_2X,	/* (0x02) MGMT Enable Register 2x */

	MV88E6XXX_CAP_G2_MGMT_EN_0X,	/* (0x03) MGMT Enable Register 0x */

	MV88E6XXX_CAP_G2_IRL_CMD,	/* (0x09) Ingress Rate Command */

	MV88E6XXX_CAP_G2_IRL_DATA,	/* (0x0a) Ingress Rate Data */

	MV88E6XXX_CAP_G2_POT,		/* (0x0f) Priority Override Table */



	/* Per VLAN Spanning Tree Unit (STU).
@@ -149,15 +147,8 @@ enum mv88e6xxx_cap { 
#define MV88E6XXX_FLAG_G2_INT		BIT_ULL(MV88E6XXX_CAP_G2_INT)

#define MV88E6XXX_FLAG_G2_MGMT_EN_2X	BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)

#define MV88E6XXX_FLAG_G2_MGMT_EN_0X	BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)

#define MV88E6XXX_FLAG_G2_IRL_CMD	BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD)

#define MV88E6XXX_FLAG_G2_IRL_DATA	BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA)

#define MV88E6XXX_FLAG_G2_POT		BIT_ULL(MV88E6XXX_CAP_G2_POT)



/* Ingress Rate Limit unit */

#define MV88E6XXX_FLAGS_IRL		\

	(MV88E6XXX_FLAG_G2_IRL_CMD |	\

	 MV88E6XXX_FLAG_G2_IRL_DATA)



/* Multi-chip Addressing Mode */

#define MV88E6XXX_FLAGS_MULTI_CHIP	\

	(MV88E6XXX_FLAG_SMI_CMD |	\
@@ -175,7 +166,6 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_G2_MGMT_EN_2X |	\

	 MV88E6XXX_FLAG_G2_MGMT_EN_0X |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6165	\
@@ -185,7 +175,6 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_G2_MGMT_EN_2X |	\

	 MV88E6XXX_FLAG_G2_MGMT_EN_0X |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6185	\
@@ -200,7 +189,6 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_G2_MGMT_EN_2X |	\

	 MV88E6XXX_FLAG_G2_MGMT_EN_0X |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6341	\
@@ -209,7 +197,6 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_GLOBAL2 |	\

	 MV88E6XXX_FLAG_G2_INT |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6351	\
@@ -219,7 +206,6 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_G2_MGMT_EN_2X |	\

	 MV88E6XXX_FLAG_G2_MGMT_EN_0X |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6352	\
@@ -230,14 +216,12 @@ enum mv88e6xxx_cap { 
	 MV88E6XXX_FLAG_G2_MGMT_EN_2X |	\

	 MV88E6XXX_FLAG_G2_MGMT_EN_0X |	\

	 MV88E6XXX_FLAG_G2_POT |	\

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



#define MV88E6XXX_FLAGS_FAMILY_6390	\

	(MV88E6XXX_FLAG_EEE |		\

	 MV88E6XXX_FLAG_GLOBAL2 |	\

	 MV88E6XXX_FLAG_G2_INT |        \

	 MV88E6XXX_FLAGS_IRL |		\

	 MV88E6XXX_FLAGS_MULTI_CHIP)



struct mv88e6xxx_ops;
@@ -358,6 +342,9 @@ struct mv88e6xxx_mdio_bus { 
};



struct mv88e6xxx_ops {

	/* Ingress Rate Limit unit (IRL) operations */

	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);



	int (*get_eeprom)(struct mv88e6xxx_chip *chip,

			  struct ethtool_eeprom *eeprom, u8 *data);

	int (*set_eeprom)(struct mv88e6xxx_chip *chip,

drivers/net/dsa/mv88e6xxx/global2.c

+221 −180

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/dsa/mv88e6xxx/global2.h

+208 −103
Original line number Diff line number Diff line 
/*

 * Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C)

 * Marvell 88E6xxx Switch Global 2 Registers support

 *

 * Copyright (c) 2008 Marvell Semiconductor

 *
@@ -17,108 +17,198 @@ 


#include "chip.h"



#define ADDR_GLOBAL2	0x1c



#define GLOBAL2_INT_SOURCE	0x00

#define GLOBAL2_INT_SOURCE_WATCHDOG	15

#define GLOBAL2_INT_MASK	0x01

#define GLOBAL2_MGMT_EN_2X	0x02

#define GLOBAL2_MGMT_EN_0X	0x03

#define GLOBAL2_FLOW_CONTROL	0x04

#define GLOBAL2_SWITCH_MGMT	0x05

#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA	BIT(15)

#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS	BIT(14)

#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG	BIT(13)

#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI	BIT(7)

#define GLOBAL2_SWITCH_MGMT_RSVD2CPU		BIT(3)

#define GLOBAL2_DEVICE_MAPPING	0x06

#define GLOBAL2_DEVICE_MAPPING_UPDATE		BIT(15)

#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT	8

#define GLOBAL2_DEVICE_MAPPING_PORT_MASK	0x0f

#define GLOBAL2_TRUNK_MASK	0x07

#define GLOBAL2_TRUNK_MASK_UPDATE		BIT(15)

#define GLOBAL2_TRUNK_MASK_NUM_SHIFT		12

#define GLOBAL2_TRUNK_MASK_HASK			BIT(11)

#define GLOBAL2_TRUNK_MAPPING	0x08

#define GLOBAL2_TRUNK_MAPPING_UPDATE		BIT(15)

#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT		11

#define GLOBAL2_IRL_CMD		0x09

#define GLOBAL2_IRL_CMD_BUSY	BIT(15)

#define GLOBAL2_IRL_CMD_OP_INIT_ALL	((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)

#define GLOBAL2_IRL_CMD_OP_INIT_SEL	((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)

#define GLOBAL2_IRL_CMD_OP_WRITE_SEL	((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)

#define GLOBAL2_IRL_CMD_OP_READ_SEL	((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)

#define GLOBAL2_IRL_DATA	0x0a

#define GLOBAL2_PVT_ADDR	0x0b

#define GLOBAL2_PVT_ADDR_BUSY	BIT(15)

#define GLOBAL2_PVT_ADDR_OP_INIT_ONES	((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)

#define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN	((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)

#define GLOBAL2_PVT_ADDR_OP_READ	((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)

#define GLOBAL2_PVT_DATA	0x0c

#define GLOBAL2_SWITCH_MAC	0x0d

#define GLOBAL2_ATU_STATS	0x0e

#define GLOBAL2_PRIO_OVERRIDE	0x0f

#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP	BIT(7)

#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT	4

#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP		BIT(3)

#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT		0

#define GLOBAL2_EEPROM_CMD		0x14

#define GLOBAL2_EEPROM_CMD_BUSY		BIT(15)

#define GLOBAL2_EEPROM_CMD_OP_WRITE	((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)

#define GLOBAL2_EEPROM_CMD_OP_READ	((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)

#define GLOBAL2_EEPROM_CMD_OP_LOAD	((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)

#define GLOBAL2_EEPROM_CMD_RUNNING	BIT(11)

#define GLOBAL2_EEPROM_CMD_WRITE_EN	BIT(10)

#define GLOBAL2_EEPROM_CMD_ADDR_MASK	0xff

#define GLOBAL2_EEPROM_DATA	0x15

#define GLOBAL2_EEPROM_ADDR	0x15 /* 6390, 6341 */

#define GLOBAL2_PTP_AVB_OP	0x16

#define GLOBAL2_PTP_AVB_DATA	0x17

#define GLOBAL2_SMI_PHY_CMD			0x18

#define GLOBAL2_SMI_PHY_CMD_BUSY		BIT(15)

#define GLOBAL2_SMI_PHY_CMD_EXTERNAL		BIT(13)

#define GLOBAL2_SMI_PHY_CMD_MODE_22		BIT(12)

#define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA	((0x1 << 10) | \

						 GLOBAL2_SMI_PHY_CMD_MODE_22 | \

						 GLOBAL2_SMI_PHY_CMD_BUSY)

#define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA	((0x2 << 10) | \

						 GLOBAL2_SMI_PHY_CMD_MODE_22 | \

						 GLOBAL2_SMI_PHY_CMD_BUSY)

#define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_ADDR	((0x0 << 10) | \

						 GLOBAL2_SMI_PHY_CMD_BUSY)

#define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA	((0x1 << 10) | \

						 GLOBAL2_SMI_PHY_CMD_BUSY)

#define GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA	((0x3 << 10) | \

						 GLOBAL2_SMI_PHY_CMD_BUSY)



#define GLOBAL2_SMI_PHY_DATA			0x19

#define GLOBAL2_SCRATCH_MISC	0x1a

#define GLOBAL2_SCRATCH_BUSY		BIT(15)

#define GLOBAL2_SCRATCH_REGISTER_SHIFT	8

#define GLOBAL2_SCRATCH_VALUE_MASK	0xff

#define GLOBAL2_WDOG_CONTROL	0x1b

#define GLOBAL2_WDOG_CONTROL_EGRESS_EVENT	BIT(7)

#define GLOBAL2_WDOG_CONTROL_RMU_TIMEOUT	BIT(6)

#define GLOBAL2_WDOG_CONTROL_QC_ENABLE		BIT(5)

#define GLOBAL2_WDOG_CONTROL_EGRESS_HISTORY	BIT(4)

#define GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE	BIT(3)

#define GLOBAL2_WDOG_CONTROL_FORCE_IRQ		BIT(2)

#define GLOBAL2_WDOG_CONTROL_HISTORY		BIT(1)

#define GLOBAL2_WDOG_CONTROL_SWRESET		BIT(0)

#define GLOBAL2_WDOG_UPDATE			BIT(15)

#define GLOBAL2_WDOG_INT_SOURCE			(0x00 << 8)

#define GLOBAL2_WDOG_INT_STATUS			(0x10 << 8)

#define GLOBAL2_WDOG_INT_ENABLE			(0x11 << 8)

#define GLOBAL2_WDOG_EVENT			(0x12 << 8)

#define GLOBAL2_WDOG_HISTORY			(0x13 << 8)

#define GLOBAL2_WDOG_DATA_MASK			0xff

#define GLOBAL2_WDOG_CUT_THROUGH		BIT(3)

#define GLOBAL2_WDOG_QUEUE_CONTROLLER		BIT(2)

#define GLOBAL2_WDOG_EGRESS			BIT(1)

#define GLOBAL2_WDOG_FORCE_IRQ			BIT(0)

#define GLOBAL2_QOS_WEIGHT	0x1c

#define GLOBAL2_MISC		0x1d

#define GLOBAL2_MISC_5_BIT_PORT	BIT(14)

#define MV88E6XXX_G2	0x1c



/* Offset 0x00: Interrupt Source Register */

#define MV88E6XXX_G2_INT_SOURCE			0x00

#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG	15



/* Offset 0x01: Interrupt Mask Register */

#define MV88E6XXX_G2_INT_MASK	0x01



/* Offset 0x02: MGMT Enable Register 2x */

#define MV88E6XXX_G2_MGMT_EN_2X		0x02



/* Offset 0x03: MGMT Enable Register 0x */

#define MV88E6XXX_G2_MGMT_EN_0X		0x03



/* Offset 0x04: Flow Control Delay Register */

#define MV88E6XXX_G2_FLOW_CTL	0x04



/* Offset 0x05: Switch Management Register */

#define MV88E6XXX_G2_SWITCH_MGMT			0x05

#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA	0x8000

#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS		0x4000

#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG		0x2000

#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI	0x0080

#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU		0x0008



/* Offset 0x06: Device Mapping Table Register */

#define MV88E6XXX_G2_DEVICE_MAPPING		0x06

#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE	0x8000

#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK	0x1f00

#define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK	0x000f



/* Offset 0x07: Trunk Mask Table Register */

#define MV88E6XXX_G2_TRUNK_MASK			0x07

#define MV88E6XXX_G2_TRUNK_MASK_UPDATE		0x8000

#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK	0x7000

#define MV88E6XXX_G2_TRUNK_MASK_HASH		0x0800



/* Offset 0x08: Trunk Mapping Table Register */

#define MV88E6XXX_G2_TRUNK_MAPPING		0x08

#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE	0x8000

#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK	0x7800



/* Offset 0x09: Ingress Rate Command Register */

#define MV88E6XXX_G2_IRL_CMD			0x09

#define MV88E6XXX_G2_IRL_CMD_BUSY		0x8000

#define MV88E6352_G2_IRL_CMD_OP_MASK		0x7000

#define MV88E6352_G2_IRL_CMD_OP_NOOP		0x0000

#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL	0x1000

#define MV88E6352_G2_IRL_CMD_OP_INIT_RES	0x2000

#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG	0x3000

#define MV88E6352_G2_IRL_CMD_OP_READ_REG	0x4000

#define MV88E6390_G2_IRL_CMD_OP_MASK		0x6000

#define MV88E6390_G2_IRL_CMD_OP_READ_REG	0x0000

#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL	0x2000

#define MV88E6390_G2_IRL_CMD_OP_INIT_RES	0x4000

#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG	0x6000

#define MV88E6352_G2_IRL_CMD_PORT_MASK		0x0f00

#define MV88E6390_G2_IRL_CMD_PORT_MASK		0x1f00

#define MV88E6XXX_G2_IRL_CMD_RES_MASK		0x00e0

#define MV88E6XXX_G2_IRL_CMD_REG_MASK		0x000f



/* Offset 0x0A: Ingress Rate Data Register */

#define MV88E6XXX_G2_IRL_DATA		0x0a

#define MV88E6XXX_G2_IRL_DATA_MASK	0xffff



/* Offset 0x0B: Cross-chip Port VLAN Register */

#define MV88E6XXX_G2_PVT_ADDR			0x0b

#define MV88E6XXX_G2_PVT_ADDR_BUSY		0x8000

#define MV88E6XXX_G2_PVT_ADDR_OP_MASK		0x7000

#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES	0x1000

#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN	0x3000

#define MV88E6XXX_G2_PVT_ADDR_OP_READ		0x4000

#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK		0x01ff



/* Offset 0x0C: Cross-chip Port VLAN Data Register */

#define MV88E6XXX_G2_PVT_DATA		0x0c

#define MV88E6XXX_G2_PVT_DATA_MASK	0x7f



/* Offset 0x0D: Switch MAC/WoL/WoF Register */

#define MV88E6XXX_G2_SWITCH_MAC			0x0d

#define MV88E6XXX_G2_SWITCH_MAC_UPDATE		0x8000

#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK	0x1f00

#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK	0x00ff



/* Offset 0x0E: ATU Stats Register */

#define MV88E6XXX_G2_ATU_STATS		0x0e



/* Offset 0x0F: Priority Override Table */

#define MV88E6XXX_G2_PRIO_OVERRIDE		0x0f

#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE	0x8000

#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET	0x1000

#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK	0x0f00

#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN	0x0080

#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK	0x0030

#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN	0x0008

#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK	0x0007



/* Offset 0x14: EEPROM Command */

#define MV88E6XXX_G2_EEPROM_CMD			0x14

#define MV88E6XXX_G2_EEPROM_CMD_BUSY		0x8000

#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK		0x7000

#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE	0x3000

#define MV88E6XXX_G2_EEPROM_CMD_OP_READ		0x4000

#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD		0x6000

#define MV88E6XXX_G2_EEPROM_CMD_RUNNING		0x0800

#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN	0x0400

#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK	0x00ff

#define MV88E6390_G2_EEPROM_CMD_DATA_MASK	0x00ff



/* Offset 0x15: EEPROM Data */

#define MV88E6352_G2_EEPROM_DATA	0x15

#define MV88E6352_G2_EEPROM_DATA_MASK	0xffff



/* Offset 0x15: EEPROM Addr */

#define MV88E6390_G2_EEPROM_ADDR	0x15

#define MV88E6390_G2_EEPROM_ADDR_MASK	0xffff



/* Offset 0x16: AVB Command Register */

#define MV88E6352_G2_AVB_CMD		0x16



/* Offset 0x17: AVB Data Register */

#define MV88E6352_G2_AVB_DATA		0x17



/* Offset 0x18: SMI PHY Command Register */

#define MV88E6XXX_G2_SMI_PHY_CMD			0x18

#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY			0x8000

#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK		0x6000

#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL		0x0000

#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL		0x2000

#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP		0x4000

#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK		0x1000

#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45		0x0000

#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22		0x1000

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK		0x0c00

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA	0x0400

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA	0x0800

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR	0x0000

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA	0x0400

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC	0x0800

#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA	0x0c00

#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK		0x03e0

#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK		0x001f

#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK		0x03ff



/* Offset 0x19: SMI PHY Data Register */

#define MV88E6XXX_G2_SMI_PHY_DATA	0x19



/* Offset 0x1A: Scratch and Misc. Register */

#define MV88E6XXX_G2_SCRATCH_MISC_MISC		0x1a

#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE	0x8000

#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK	0x7f00

#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK	0x00ff



/* Offset 0x1B: Watch Dog Control Register */

#define MV88E6352_G2_WDOG_CTL			0x1b

#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT	0x0080

#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT	0x0040

#define MV88E6352_G2_WDOG_CTL_QC_ENABLE		0x0020

#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY	0x0010

#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE	0x0008

#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ		0x0004

#define MV88E6352_G2_WDOG_CTL_HISTORY		0x0002

#define MV88E6352_G2_WDOG_CTL_SWRESET		0x0001



/* Offset 0x1B: Watch Dog Control Register */

#define MV88E6390_G2_WDOG_CTL				0x1b

#define MV88E6390_G2_WDOG_CTL_UPDATE			0x8000

#define MV88E6390_G2_WDOG_CTL_PTR_MASK			0x7f00

#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE		0x0000

#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS		0x1000

#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE		0x1100

#define MV88E6390_G2_WDOG_CTL_PTR_EVENT			0x1200

#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY		0x1300

#define MV88E6390_G2_WDOG_CTL_DATA_MASK			0x00ff

#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH		0x0008

#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER		0x0004

#define MV88E6390_G2_WDOG_CTL_EGRESS			0x0002

#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ			0x0001



/* Offset 0x1C: QoS Weights Register */

#define MV88E6XXX_G2_QOS_WEIGHTS		0x1c

#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE		0x8000

#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK	0x3f00

#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK	0x7f00

#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK	0x00ff



/* Offset 0x1D: Misc Register */

#define MV88E6XXX_G2_MISC		0x1d

#define MV88E6XXX_G2_MISC_5_BIT_PORT	0x4000

#define MV88E6352_G2_NOEGR_POLICY	0x2000

#define MV88E6390_G2_LAG_ID_4		0x2000



#ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
@@ -127,6 +217,9 @@ static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 
	return 0;

}



int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);

int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);



int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,

			      struct mii_bus *bus,

			      int addr, int reg, u16 *val);
@@ -169,6 +262,18 @@ static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 
	return 0;

}



static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,

					    int port)

{

	return -EOPNOTSUPP;

}



static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,

					    int port)

{

	return -EOPNOTSUPP;

}



static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,

					    struct mii_bus *bus,

					    int addr, int reg, u16 *val)

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