Commit d9e48dc2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pwm/for-5.5-rc1' of... 

Merge tag 'pwm/for-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "Various changes and minor fixes across a couple of drivers"

* tag 'pwm/for-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: stm32: Pass breakinput instead of its values
  pwm: stm32: Remove clutter from ternary operator
  pwm: stm32: Validate breakinput data from DT
  pwm: Update comment on struct pwm_ops::apply
  pwm: sun4i: Fix incorrect calculation of duty_cycle/period
  pwm: stm32: Add power management support
  pwm: stm32: Split breakinput apply routine to ease PM support
  dt-bindings: pwm-stm32: Document pinctrl sleep state
  pwm: sun4i: Drop redundant assignment to variable pval
  dt-bindings: pwm: mediatek: Remove gratuitous compatible string for MT7629
parents fb3da48a 9e1b4999

Documentation/devicetree/bindings/pwm/pwm-mediatek.txt

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Required properties: 
   - "mediatek,mt7622-pwm": found on mt7622 SoC.

   - "mediatek,mt7623-pwm": found on mt7623 SoC.

   - "mediatek,mt7628-pwm": found on mt7628 SoC.

   - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.

   - "mediatek,mt7629-pwm": found on mt7629 SoC.

   - "mediatek,mt8516-pwm": found on mt8516 SoC.

 - reg: physical base address and length of the controller's registers.

 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of

drivers/pwm/pwm-stm32.c

+82 −30
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/mfd/stm32-timers.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/pinctrl/consumer.h>

#include <linux/platform_device.h>

#include <linux/pwm.h>
@@ -19,6 +20,12 @@ 
#define CCMR_CHANNEL_MASK  0xFF

#define MAX_BREAKINPUT 2



struct stm32_breakinput {

	u32 index;

	u32 level;

	u32 filter;

};



struct stm32_pwm {

	struct pwm_chip chip;

	struct mutex lock; /* protect pwm config/enable */
@@ -26,15 +33,11 @@ struct stm32_pwm { 
	struct regmap *regmap;

	u32 max_arr;

	bool have_complementary_output;

	struct stm32_breakinput breakinputs[MAX_BREAKINPUT];

	unsigned int num_breakinputs;

	u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */

};



struct stm32_breakinput {

	u32 index;

	u32 level;

	u32 filter;

};



static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)

{

	return container_of(chip, struct stm32_pwm, chip);
@@ -488,22 +491,19 @@ static const struct pwm_ops stm32pwm_ops = { 
};



static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,

				    int index, int level, int filter)

				    const struct stm32_breakinput *bi)

{

	u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;

	int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;

	u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF

				: TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;

	u32 bdtr = bke;

	u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);

	u32 bke = TIM_BDTR_BKE(bi->index);

	u32 bkp = TIM_BDTR_BKP(bi->index);

	u32 bkf = TIM_BDTR_BKF(bi->index);

	u32 mask = bkf | bkp | bke;

	u32 bdtr;



	/*

	 * The both bits could be set since only one will be wrote

	 * due to mask value.

	 */

	if (level)

		bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;

	bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;



	bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;

	if (bi->level)

		bdtr |= bkp;



	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
@@ -512,11 +512,25 @@ static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, 
	return (bdtr & bke) ? 0 : -EINVAL;

}



static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,

static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)

{

	unsigned int i;

	int ret;



	for (i = 0; i < priv->num_breakinputs; i++) {

		ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);

		if (ret < 0)

			return ret;

	}



	return 0;

}



static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,

				       struct device_node *np)

{

	struct stm32_breakinput breakinput[MAX_BREAKINPUT];

	int nb, ret, i, array_size;

	int nb, ret, array_size;

	unsigned int i;



	nb = of_property_count_elems_of_size(np, "st,breakinput",

					     sizeof(struct stm32_breakinput));
@@ -531,20 +545,21 @@ static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv, 
	if (nb > MAX_BREAKINPUT)

		return -EINVAL;



	priv->num_breakinputs = nb;

	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);

	ret = of_property_read_u32_array(np, "st,breakinput",

					 (u32 *)breakinput, array_size);

					 (u32 *)priv->breakinputs, array_size);

	if (ret)

		return ret;



	for (i = 0; i < nb && !ret; i++) {

		ret = stm32_pwm_set_breakinput(priv,

					       breakinput[i].index,

					       breakinput[i].level,

					       breakinput[i].filter);

	for (i = 0; i < priv->num_breakinputs; i++) {

		if (priv->breakinputs[i].index > 1 ||

		    priv->breakinputs[i].level > 1 ||

		    priv->breakinputs[i].filter > 15)

			return -EINVAL;

	}



	return ret;

	return stm32_pwm_apply_breakinputs(priv);

}



static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
@@ -614,7 +629,7 @@ static int stm32_pwm_probe(struct platform_device *pdev) 
	if (!priv->regmap || !priv->clk)

		return -EINVAL;



	ret = stm32_pwm_apply_breakinputs(priv, np);

	ret = stm32_pwm_probe_breakinputs(priv, np);

	if (ret)

		return ret;
@@ -647,6 +662,42 @@ static int stm32_pwm_remove(struct platform_device *pdev) 
	return 0;

}



static int __maybe_unused stm32_pwm_suspend(struct device *dev)

{

	struct stm32_pwm *priv = dev_get_drvdata(dev);

	unsigned int i;

	u32 ccer, mask;



	/* Look for active channels */

	ccer = active_channels(priv);



	for (i = 0; i < priv->chip.npwm; i++) {

		mask = TIM_CCER_CC1E << (i * 4);

		if (ccer & mask) {

			dev_err(dev, "PWM %u still in use by consumer %s\n",

				i, priv->chip.pwms[i].label);

			return -EBUSY;

		}

	}



	return pinctrl_pm_select_sleep_state(dev);

}



static int __maybe_unused stm32_pwm_resume(struct device *dev)

{

	struct stm32_pwm *priv = dev_get_drvdata(dev);

	int ret;



	ret = pinctrl_pm_select_default_state(dev);

	if (ret)

		return ret;



	/* restore breakinput registers that may have been lost in low power */

	return stm32_pwm_apply_breakinputs(priv);

}



static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);



static const struct of_device_id stm32_pwm_of_match[] = {

	{ .compatible = "st,stm32-pwm",	},

	{ /* end node */ },
@@ -659,6 +710,7 @@ static struct platform_driver stm32_pwm_driver = { 
	.driver	= {

		.name = "stm32-pwm",

		.of_match_table = stm32_pwm_of_match,

		.pm = &stm32_pwm_pm_ops,

	},

};

module_platform_driver(stm32_pwm_driver);

drivers/pwm/pwm-sun4i.c

+2 −3
Original line number Diff line number Diff line
@@ -137,10 +137,10 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, 


	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));



	tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);

	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);



	tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);

	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

}
@@ -156,7 +156,6 @@ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, 
	if (sun4i_pwm->data->has_prescaler_bypass) {

		/* First, test without any prescaler when available */

		prescaler = PWM_PRESCAL_MASK;

		pval = 1;

		/*

		 * When not using any prescaler, the clock period in nanoseconds

		 * is not an integer so round it half up instead of

include/linux/mfd/stm32-timers.h

+4 −8
Original line number Diff line number Diff line
@@ -70,14 +70,11 @@ 
#define TIM_CCER_CC4E	BIT(12)	/* Capt/Comp 4  out Ena    */

#define TIM_CCER_CC4P	BIT(13)	/* Capt/Comp 4  Polarity   */

#define TIM_CCER_CCXE	(BIT(0) | BIT(4) | BIT(8) | BIT(12))

#define TIM_BDTR_BKE	BIT(12) /* Break input enable	   */

#define TIM_BDTR_BKP	BIT(13) /* Break input polarity	   */

#define TIM_BDTR_BKE(x)	BIT(12 + (x) * 12) /* Break input enable */

#define TIM_BDTR_BKP(x)	BIT(13 + (x) * 12) /* Break input polarity */

#define TIM_BDTR_AOE	BIT(14)	/* Automatic Output Enable */

#define TIM_BDTR_MOE	BIT(15)	/* Main Output Enable      */

#define TIM_BDTR_BKF	(BIT(16) | BIT(17) | BIT(18) | BIT(19))

#define TIM_BDTR_BK2F	(BIT(20) | BIT(21) | BIT(22) | BIT(23))

#define TIM_BDTR_BK2E	BIT(24) /* Break 2 input enable	   */

#define TIM_BDTR_BK2P	BIT(25) /* Break 2 input polarity  */

#define TIM_BDTR_BKF(x)	(0xf << (16 + (x) * 4))

#define TIM_DCR_DBA	GENMASK(4, 0)	/* DMA base addr */

#define TIM_DCR_DBL	GENMASK(12, 8)	/* DMA burst len */
@@ -87,8 +84,7 @@ 
#define TIM_CR2_MMS2_SHIFT	20

#define TIM_SMCR_TS_SHIFT	4

#define TIM_BDTR_BKF_MASK	0xF

#define TIM_BDTR_BKF_SHIFT	16

#define TIM_BDTR_BK2F_SHIFT	20

#define TIM_BDTR_BKF_SHIFT(x)	(16 + (x) * 4)



enum stm32_timers_dmas {

	STM32_TIMERS_DMA_CH1,

include/linux/pwm.h

+1 −4
Original line number Diff line number Diff line
@@ -243,10 +243,7 @@ pwm_set_relative_duty_cycle(struct pwm_state *state, unsigned int duty_cycle, 
 * @request: optional hook for requesting a PWM

 * @free: optional hook for freeing a PWM

 * @capture: capture and report PWM signal

 * @apply: atomically apply a new PWM config. The state argument

 *	   should be adjusted with the real hardware config (if the

 *	   approximate the period or duty_cycle value, state should

 *	   reflect it)

 * @apply: atomically apply a new PWM config

 * @get_state: get the current PWM state. This function is only

 *	       called once per PWM device when the PWM chip is

 *	       registered.

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