Merge 4.15-rc4 into usb-next (d9e3d899) · Commits · 戴 / test

Documentation/arm64/silicon-errata.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -75,3 +75,4 @@ stable kernels.
		\| Qualcomm Tech. \| Falkor v1 \| E1003 \| QCOM_FALKOR_ERRATUM_1003 \|
		\| Qualcomm Tech. \| Falkor v1 \| E1009 \| QCOM_FALKOR_ERRATUM_1009 \|
		\| Qualcomm Tech. \| QDF2400 ITS \| E0065 \| QCOM_QDF2400_ERRATUM_0065 \|
		\| Qualcomm Tech. \| Falkor v{1,2} \| E1041 \| QCOM_FALKOR_ERRATUM_1041 \|

Documentation/cgroup-v2.txt

+7 −0

Original line number	Diff line number	Diff line
		@@ -898,6 +898,13 @@ controller implements weight and absolute bandwidth limit models for
		normal scheduling policy and absolute bandwidth allocation model for
		realtime scheduling policy.

		WARNING: cgroup2 doesn't yet support control of realtime processes and
		the cpu controller can only be enabled when all RT processes are in
		the root cgroup. Be aware that system management software may already
		have placed RT processes into nonroot cgroups during the system boot
		process, and these processes may need to be moved to the root cgroup
		before the cpu controller can be enabled.


		CPU Interface Files
		~~~~~~~~~~~~~~~~~~~

Documentation/core-api/genericirq.rst

+8 −8

Original line number	Diff line number	Diff line
		@@ -225,9 +225,9 @@ interrupts.

		The following control flow is implemented (simplified excerpt)::

		:c:func:`desc->irq_data.chip->irq_mask_ack`;
		desc->irq_data.chip->irq_mask_ack();
		handle_irq_event(desc->action);
		:c:func:`desc->irq_data.chip->irq_unmask`;
		desc->irq_data.chip->irq_unmask();


		Default Fast EOI IRQ flow handler
		@@ -239,7 +239,7 @@ which only need an EOI at the end of the handler.
		The following control flow is implemented (simplified excerpt)::

		handle_irq_event(desc->action);
		:c:func:`desc->irq_data.chip->irq_eoi`;
		desc->irq_data.chip->irq_eoi();


		Default Edge IRQ flow handler
		@@ -251,15 +251,15 @@ interrupts.
		The following control flow is implemented (simplified excerpt)::

		if (desc->status & running) {
		:c:func:`desc->irq_data.chip->irq_mask_ack`;
		desc->irq_data.chip->irq_mask_ack();
		desc->status \|= pending \| masked;
		return;
		}
		:c:func:`desc->irq_data.chip->irq_ack`;
		desc->irq_data.chip->irq_ack();
		desc->status \|= running;
		do {
		if (desc->status & masked)
		:c:func:`desc->irq_data.chip->irq_unmask`;
		desc->irq_data.chip->irq_unmask();
		desc->status &= ~pending;
		handle_irq_event(desc->action);
		} while (status & pending);
		@@ -293,10 +293,10 @@ simplified version without locking.
		The following control flow is implemented (simplified excerpt)::

		if (desc->irq_data.chip->irq_ack)
		:c:func:`desc->irq_data.chip->irq_ack`;
		desc->irq_data.chip->irq_ack();
		handle_irq_event(desc->action);
		if (desc->irq_data.chip->irq_eoi)
		:c:func:`desc->irq_data.chip->irq_eoi`;
		desc->irq_data.chip->irq_eoi();


		EOI Edge IRQ flow handler

Documentation/devicetree/bindings/arm/ccn.txt

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		@@ -15,7 +15,7 @@ Required properties:

		Example:

		ccn@0x2000000000 {
		ccn@2000000000 {
		compatible = "arm,ccn-504";
		reg = <0x20 0x00000000 0 0x1000000>;
		interrupts = <0 181 4>;

Documentation/devicetree/bindings/arm/omap/crossbar.txt

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		@@ -49,7 +49,7 @@ An interrupt consumer on an SoC using crossbar will use:
		interrupts = <GIC_SPI request_number interrupt_level>

		Example:
		device_x@0x4a023000 {
		device_x@4a023000 {
		/* Crossbar 8 used */
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		...

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