Merge branch 'net-phy-add-and-use-further-MMD-accessors' (d9b5a675) · Commits · 戴 / test

drivers/net/phy/dp83867.c

+17 −30

Original line number	Original line	Diff line number	Diff line
	@@ -127,17 +127,13 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
	{		{
	struct dp83867_private *dp83867 =		struct dp83867_private *dp83867 =
	(struct dp83867_private *)phydev->priv;		(struct dp83867_private *)phydev->priv;
	u16 val;

	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);

	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)		if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
	val \|= DP83867_CFG4_PORT_MIRROR_EN;		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
			DP83867_CFG4_PORT_MIRROR_EN);
	else		else
	val &= ~DP83867_CFG4_PORT_MIRROR_EN;		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
			DP83867_CFG4_PORT_MIRROR_EN);
	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);

	return 0;		return 0;
	}		}

	@@ -222,11 +218,9 @@ static int dp83867_config_init(struct phy_device *phydev)
	}		}

	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */		/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	if (dp83867->rxctrl_strap_quirk) {		if (dp83867->rxctrl_strap_quirk)
	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
	val &= ~BIT(7);		BIT(7));
	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
	}

	if (phy_interface_is_rgmii(phydev)) {		if (phy_interface_is_rgmii(phydev)) {
	val = phy_read(phydev, MII_DP83867_PHYCTRL);		val = phy_read(phydev, MII_DP83867_PHYCTRL);
	@@ -275,17 +269,11 @@ static int dp83867_config_init(struct phy_device *phydev)
	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
	delay);		delay);

	if (dp83867->io_impedance >= 0) {		if (dp83867->io_impedance >= 0)
	val = phy_read_mmd(phydev, DP83867_DEVADDR,		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
	DP83867_IO_MUX_CFG);		DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
			dp83867->io_impedance &
	val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;		DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
	val \|= dp83867->io_impedance &
	DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;

	phy_write_mmd(phydev, DP83867_DEVADDR,
	DP83867_IO_MUX_CFG, val);
	}
	}		}

	/* Enable Interrupt output INT_OE in CFG3 register */		/* Enable Interrupt output INT_OE in CFG3 register */
	@@ -299,12 +287,11 @@ static int dp83867_config_init(struct phy_device *phydev)
	dp83867_config_port_mirroring(phydev);		dp83867_config_port_mirroring(phydev);

	/* Clock output selection if muxing property is set */		/* Clock output selection if muxing property is set */
	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {		if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
	val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;		DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
	val \|= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);		dp83867->clk_output_sel <<
	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);		DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
	}

	return 0;		return 0;
	}		}

drivers/net/phy/dp83tc811.c

+4 −11

Original line number	Original line	Diff line number	Diff line
	@@ -144,11 +144,8 @@ static int dp83811_set_wol(struct phy_device *phydev,
	phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
	value);		value);
	} else {		} else {
	value = phy_read_mmd(phydev, DP83811_DEVADDR,		phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
	MII_DP83811_WOL_CFG);		DP83811_WOL_EN);
	value &= ~DP83811_WOL_EN;
	phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
	value);
	}		}

	return 0;		return 0;
	@@ -328,13 +325,9 @@ static int dp83811_suspend(struct phy_device *phydev)

	static int dp83811_resume(struct phy_device *phydev)		static int dp83811_resume(struct phy_device *phydev)
	{		{
	int value;

	genphy_resume(phydev);		genphy_resume(phydev);

	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);		phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,

	phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value \|
	DP83811_WOL_CLR_INDICATION);		DP83811_WOL_CLR_INDICATION);

	return 0;		return 0;

drivers/net/phy/marvell10g.c

+10 −28

Original line number	Original line	Diff line number	Diff line
	@@ -58,24 +58,6 @@ struct mv3310_priv {
	char *hwmon_name;		char *hwmon_name;
	};		};

	static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
	u16 mask, u16 bits)
	{
	int old, val, ret;

	old = phy_read_mmd(phydev, devad, reg);
	if (old < 0)
	return old;

	val = (old & ~mask) \| (bits & mask);
	if (val == old)
	return 0;

	ret = phy_write_mmd(phydev, devad, reg, val);

	return ret < 0 ? ret : 1;
	}

	#ifdef CONFIG_HWMON		#ifdef CONFIG_HWMON
	static umode_t mv3310_hwmon_is_visible(const void *data,		static umode_t mv3310_hwmon_is_visible(const void *data,
	enum hwmon_sensor_types type,		enum hwmon_sensor_types type,
	@@ -159,7 +141,7 @@ static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
	return ret;		return ret;

	val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;		val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
	ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
	MV_V2_TEMP_CTRL_MASK, val);		MV_V2_TEMP_CTRL_MASK, val);

	return ret < 0 ? ret : 0;		return ret < 0 ? ret : 0;
	@@ -363,7 +345,7 @@ static int mv3310_config_aneg(struct phy_device *phydev)
	linkmode_and(phydev->advertising, phydev->advertising,		linkmode_and(phydev->advertising, phydev->advertising,
	phydev->supported);		phydev->supported);

	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,		ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
	ADVERTISE_ALL \| ADVERTISE_100BASE4 \|		ADVERTISE_ALL \| ADVERTISE_100BASE4 \|
	ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM,		ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM,
	linkmode_adv_to_mii_adv_t(phydev->advertising));		linkmode_adv_to_mii_adv_t(phydev->advertising));
	@@ -373,7 +355,7 @@ static int mv3310_config_aneg(struct phy_device *phydev)
	changed = true;		changed = true;

	reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);		reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
	ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,		ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
	ADVERTISE_1000FULL \| ADVERTISE_1000HALF, reg);		ADVERTISE_1000FULL \| ADVERTISE_1000HALF, reg);
	if (ret < 0)		if (ret < 0)
	return ret;		return ret;
	@@ -387,7 +369,7 @@ static int mv3310_config_aneg(struct phy_device *phydev)
	else		else
	reg = 0;		reg = 0;

	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,		ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
	MDIO_AN_10GBT_CTRL_ADV10G, reg);		MDIO_AN_10GBT_CTRL_ADV10G, reg);
	if (ret < 0)		if (ret < 0)
	return ret;		return ret;

drivers/net/phy/phy-c45.c

+4 −17

Original line number	Original line	Diff line number	Diff line
	@@ -75,15 +75,9 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
	*/		*/
	int genphy_c45_an_disable_aneg(struct phy_device *phydev)		int genphy_c45_an_disable_aneg(struct phy_device *phydev)
	{		{
	int val;

	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
	if (val < 0)
	return val;

	val &= ~(MDIO_AN_CTRL1_ENABLE \| MDIO_AN_CTRL1_RESTART);

	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);		return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
			MDIO_AN_CTRL1_ENABLE \| MDIO_AN_CTRL1_RESTART);
	}		}
	EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);		EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);

	@@ -97,15 +91,8 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
	*/		*/
	int genphy_c45_restart_aneg(struct phy_device *phydev)		int genphy_c45_restart_aneg(struct phy_device *phydev)
	{		{
	int val;		return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
			MDIO_AN_CTRL1_ENABLE \| MDIO_AN_CTRL1_RESTART);
	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
	if (val < 0)
	return val;

	val \|= MDIO_AN_CTRL1_ENABLE \| MDIO_AN_CTRL1_RESTART;

	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
	}		}
	EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);		EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);

drivers/net/phy/phy-core.c

+103 −13

Original line number	Original line	Diff line number	Diff line
	@@ -414,15 +414,15 @@ static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
	}		}

	/**		/**
	* phy_read_mmd - Convenience function for reading a register		* __phy_read_mmd - Convenience function for reading a register
	* from an MMD on a given PHY.		* from an MMD on a given PHY.
	* @phydev: The phy_device struct		* @phydev: The phy_device struct
	* @devad: The MMD to read from (0..31)		* @devad: The MMD to read from (0..31)
	* @regnum: The register on the MMD to read (0..65535)		* @regnum: The register on the MMD to read (0..65535)
	*		*
	* Same rules as for phy_read();		* Same rules as for __phy_read();
	*/		*/
	int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)		int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
	{		{
	int val;		int val;

	@@ -434,33 +434,52 @@ int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
	} else if (phydev->is_c45) {		} else if (phydev->is_c45) {
	u32 addr = MII_ADDR_C45 \| (devad << 16) \| (regnum & 0xffff);		u32 addr = MII_ADDR_C45 \| (devad << 16) \| (regnum & 0xffff);

	val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);		val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);
	} else {		} else {
	struct mii_bus *bus = phydev->mdio.bus;		struct mii_bus *bus = phydev->mdio.bus;
	int phy_addr = phydev->mdio.addr;		int phy_addr = phydev->mdio.addr;

	mutex_lock(&bus->mdio_lock);
	mmd_phy_indirect(bus, phy_addr, devad, regnum);		mmd_phy_indirect(bus, phy_addr, devad, regnum);

	/* Read the content of the MMD's selected register */		/* Read the content of the MMD's selected register */
	val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);		val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
	mutex_unlock(&bus->mdio_lock);
	}		}
	return val;		return val;
	}		}
			EXPORT_SYMBOL(__phy_read_mmd);

			/**
			* phy_read_mmd - Convenience function for reading a register
			* from an MMD on a given PHY.
			* @phydev: The phy_device struct
			* @devad: The MMD to read from
			* @regnum: The register on the MMD to read
			*
			* Same rules as for phy_read();
			*/
			int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
			{
			int ret;

			mutex_lock(&phydev->mdio.bus->mdio_lock);
			ret = __phy_read_mmd(phydev, devad, regnum);
			mutex_unlock(&phydev->mdio.bus->mdio_lock);

			return ret;
			}
	EXPORT_SYMBOL(phy_read_mmd);		EXPORT_SYMBOL(phy_read_mmd);

	/**		/**
	* phy_write_mmd - Convenience function for writing a register		* __phy_write_mmd - Convenience function for writing a register
	* on an MMD on a given PHY.		* on an MMD on a given PHY.
	* @phydev: The phy_device struct		* @phydev: The phy_device struct
	* @devad: The MMD to read from		* @devad: The MMD to read from
	* @regnum: The register on the MMD to read		* @regnum: The register on the MMD to read
	* @val: value to write to @regnum		* @val: value to write to @regnum
	*		*
	* Same rules as for phy_write();		* Same rules as for __phy_write();
	*/		*/
	int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)		int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
	{		{
	int ret;		int ret;

	@@ -472,23 +491,43 @@ int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
	} else if (phydev->is_c45) {		} else if (phydev->is_c45) {
	u32 addr = MII_ADDR_C45 \| (devad << 16) \| (regnum & 0xffff);		u32 addr = MII_ADDR_C45 \| (devad << 16) \| (regnum & 0xffff);

	ret = mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,		ret = __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
	addr, val);		addr, val);
	} else {		} else {
	struct mii_bus *bus = phydev->mdio.bus;		struct mii_bus *bus = phydev->mdio.bus;
	int phy_addr = phydev->mdio.addr;		int phy_addr = phydev->mdio.addr;

	mutex_lock(&bus->mdio_lock);
	mmd_phy_indirect(bus, phy_addr, devad, regnum);		mmd_phy_indirect(bus, phy_addr, devad, regnum);

	/* Write the data into MMD's selected register */		/* Write the data into MMD's selected register */
	__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);		__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
	mutex_unlock(&bus->mdio_lock);

	ret = 0;		ret = 0;
	}		}
	return ret;		return ret;
	}		}
			EXPORT_SYMBOL(__phy_write_mmd);

			/**
			* phy_write_mmd - Convenience function for writing a register
			* on an MMD on a given PHY.
			* @phydev: The phy_device struct
			* @devad: The MMD to read from
			* @regnum: The register on the MMD to read
			* @val: value to write to @regnum
			*
			* Same rules as for phy_write();
			*/
			int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
			{
			int ret;

			mutex_lock(&phydev->mdio.bus->mdio_lock);
			ret = __phy_write_mmd(phydev, devad, regnum, val);
			mutex_unlock(&phydev->mdio.bus->mdio_lock);

			return ret;
			}
	EXPORT_SYMBOL(phy_write_mmd);		EXPORT_SYMBOL(phy_write_mmd);

	/**		/**
	@@ -538,6 +577,57 @@ int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
	}		}
	EXPORT_SYMBOL_GPL(phy_modify);		EXPORT_SYMBOL_GPL(phy_modify);

			/**
			* __phy_modify_mmd - Convenience function for modifying a register on MMD
			* @phydev: the phy_device struct
			* @devad: the MMD containing register to modify
			* @regnum: register number to modify
			* @mask: bit mask of bits to clear
			* @set: new value of bits set in mask to write to @regnum
			*
			* Unlocked helper function which allows a MMD register to be modified as
			* new register value = (old register value & ~mask) \| set
			*/
			int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
			u16 mask, u16 set)
			{
			int ret;

			ret = __phy_read_mmd(phydev, devad, regnum);
			if (ret < 0)
			return ret;

			ret = __phy_write_mmd(phydev, devad, regnum, (ret & ~mask) \| set);

			return ret < 0 ? ret : 0;
			}
			EXPORT_SYMBOL_GPL(__phy_modify_mmd);

			/**
			* phy_modify_mmd - Convenience function for modifying a register on MMD
			* @phydev: the phy_device struct
			* @devad: the MMD containing register to modify
			* @regnum: register number to modify
			* @mask: bit mask of bits to clear
			* @set: new value of bits set in mask to write to @regnum
			*
			* NOTE: MUST NOT be called from interrupt context,
			* because the bus read/write functions may wait for an interrupt
			* to conclude the operation.
			*/
			int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
			u16 mask, u16 set)
			{
			int ret;

			mutex_lock(&phydev->mdio.bus->mdio_lock);
			ret = __phy_modify_mmd(phydev, devad, regnum, mask, set);
			mutex_unlock(&phydev->mdio.bus->mdio_lock);

			return ret;
			}
			EXPORT_SYMBOL_GPL(phy_modify_mmd);

	static int __phy_read_page(struct phy_device *phydev)		static int __phy_read_page(struct phy_device *phydev)
	{		{
	return phydev->drv->read_page(phydev);		return phydev->drv->read_page(phydev);

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