Commit d98de8ef authored by Vivek Gautam's avatar Vivek Gautam Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: msm8996: Add Coresight support 



Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.

This also adds coresight cpu debug nodes.

Signed-off-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: default avatarSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 783abfa2

arch/arm64/boot/dts/qcom/msm8996.dtsi

+468 −0
Original line number Diff line number Diff line
@@ -633,6 +633,474 @@ 
			reg = <0x300000 0x90000>;

		};



		stm@3002000 {

			compatible = "arm,coresight-stm", "arm,primecell";

			reg = <0x3002000 0x1000>,

			      <0x8280000 0x180000>;

			reg-names = "stm-base", "stm-stimulus-base";



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			out-ports {

				port {

					stm_out: endpoint {

						remote-endpoint =

						  <&funnel0_in>;

					};

				};

			};

		};



		tpiu@3020000 {

			compatible = "arm,coresight-tpiu", "arm,primecell";

			reg = <0x3020000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				port {

					tpiu_in: endpoint {

						remote-endpoint =

						  <&replicator_out1>;

					};

				};

			};

		};



		funnel@3021000 {

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3021000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@7 {

					reg = <7>;

					funnel0_in: endpoint {

						remote-endpoint =

						  <&stm_out>;

					};

				};

			};



			out-ports {

				port {

					funnel0_out: endpoint {

						remote-endpoint =

						  <&merge_funnel_in0>;

					};

				};

			};

		};



		funnel@3022000 {

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3022000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@6 {

					reg = <6>;

					funnel1_in: endpoint {

						remote-endpoint =

						  <&apss_merge_funnel_out>;

					};

				};

			};



			out-ports {

				port {

					funnel1_out: endpoint {

						remote-endpoint =

						  <&merge_funnel_in1>;

					};

				};

			};

		};



		funnel@3023000 {

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3023000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";





			out-ports {

				port {

					funnel2_out: endpoint {

						remote-endpoint =

						  <&merge_funnel_in2>;

					};

				};

			};

		};



		funnel@3025000 {

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3025000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					merge_funnel_in0: endpoint {

						remote-endpoint =

						  <&funnel0_out>;

					};

				};



				port@1 {

					reg = <1>;

					merge_funnel_in1: endpoint {

						remote-endpoint =

						  <&funnel1_out>;

					};

				};



				port@2 {

					reg = <2>;

					merge_funnel_in2: endpoint {

						remote-endpoint =

						  <&funnel2_out>;

					};

				};

			};



			out-ports {

				port {

					merge_funnel_out: endpoint {

						remote-endpoint =

						  <&etf_in>;

					};

				};

			};

		};



		replicator@3026000 {

			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";

			reg = <0x3026000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				port {

					replicator_in: endpoint {

						remote-endpoint =

						  <&etf_out>;

					};

				};

			};



			out-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					replicator_out0: endpoint {

						remote-endpoint =

						  <&etr_in>;

					};

				};



				port@1 {

					reg = <1>;

					replicator_out1: endpoint {

						remote-endpoint =

						  <&tpiu_in>;

					};

				};

			};

		};



		etf@3027000 {

			compatible = "arm,coresight-tmc", "arm,primecell";

			reg = <0x3027000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				port {

					etf_in: endpoint {

						remote-endpoint =

						  <&merge_funnel_out>;

					};

				};

			};



			out-ports {

				port {

					etf_out: endpoint {

						remote-endpoint =

						  <&replicator_in>;

					};

				};

			};

		};



		etr@3028000 {

			compatible = "arm,coresight-tmc", "arm,primecell";

			reg = <0x3028000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";

			arm,scatter-gather;



			in-ports {

				port {

					etr_in: endpoint {

						remote-endpoint =

						  <&replicator_out0>;

					};

				};

			};

		};



		debug@3810000 {

			compatible = "arm,coresight-cpu-debug", "arm,primecell";

			reg = <0x3810000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			cpu = <&CPU0>;

		};



		etm@3840000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0x3840000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			cpu = <&CPU0>;



			out-ports {

				port {

					etm0_out: endpoint {

						remote-endpoint =

						  <&apss_funnel0_in0>;

					};

				};

			};

		};



		debug@3910000 {

			compatible = "arm,coresight-cpu-debug", "arm,primecell";

			reg = <0x3910000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			cpu = <&CPU1>;

		};



		etm@3940000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0x3940000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			cpu = <&CPU1>;



			out-ports {

				port {

					etm1_out: endpoint {

						remote-endpoint =

						  <&apss_funnel0_in1>;

					};

				};

			};

		};



		funnel@39b0000 { /* APSS Funnel 0 */

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x39b0000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					apss_funnel0_in0: endpoint {

						remote-endpoint = <&etm0_out>;

					};

				};



				port@1 {

					reg = <1>;

					apss_funnel0_in1: endpoint {

						remote-endpoint = <&etm1_out>;

					};

				};

			};



			out-ports {

				port {

					apss_funnel0_out: endpoint {

						remote-endpoint =

						  <&apss_merge_funnel_in0>;

					};

				};

			};

		};



		debug@3a10000 {

			compatible = "arm,coresight-cpu-debug", "arm,primecell";

			reg = <0x3a10000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			cpu = <&CPU2>;

		};



		etm@3a40000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0x3a40000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			cpu = <&CPU2>;



			out-ports {

				port {

					etm2_out: endpoint {

						remote-endpoint =

						  <&apss_funnel1_in0>;

					};

				};

			};

		};



		debug@3b10000 {

			compatible = "arm,coresight-cpu-debug", "arm,primecell";

			reg = <0x3b10000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			cpu = <&CPU3>;

		};



		etm@3b40000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0x3b40000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			cpu = <&CPU3>;



			out-ports {

				port {

					etm3_out: endpoint {

						remote-endpoint =

						  <&apss_funnel1_in1>;

					};

				};

			};

		};



		funnel@3bb0000 { /* APSS Funnel 1 */

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3bb0000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					apss_funnel1_in0: endpoint {

						remote-endpoint = <&etm2_out>;

					};

				};



				port@1 {

					reg = <1>;

					apss_funnel1_in1: endpoint {

						remote-endpoint = <&etm3_out>;

					};

				};

			};



			out-ports {

				port {

					apss_funnel1_out: endpoint {

						remote-endpoint =

						  <&apss_merge_funnel_in1>;

					};

				};

			};

		};



		funnel@3bc0000 {

			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

			reg = <0x3bc0000 0x1000>;



			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

			clock-names = "apb_pclk", "atclk";



			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					apss_merge_funnel_in0: endpoint {

						remote-endpoint =

						  <&apss_funnel0_out>;

					};

				};



				port@1 {

					reg = <1>;

					apss_merge_funnel_in1: endpoint {

						remote-endpoint =

						  <&apss_funnel1_out>;

					};

				};

			};



			out-ports {

				port {

					apss_merge_funnel_out: endpoint {

						remote-endpoint =

						  <&funnel1_in>;

					};

				};

			};

		};



		kryocc: clock-controller@6400000 {

			compatible = "qcom,apcc-msm8996";

			reg = <0x6400000 0x90000>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE