Commit d988f887 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "Fixes for various clk driver issues that happened because of code we
  merged this merge window.

  The Amlogic driver was missing some flags causing rates to be rounded
  improperly or clk_set_rate() to fail. The Samsung driver wasn't
  freeing everything on error paths and improperly saving/restoring PLL
  state across suspend/resume. The at91 driver was calling msleep() too
  early when scheduling hadn't started, so we put in place a quick
  solution until we can handle this sort of problem in the core
  framework.

  There were also problems with the Allwinner driver and operator
  precedence being incorrect causing subtle bugs. Finally, the TI driver
  was duplicating aliases and not delaying long enough leading to some
  unexpected timeouts"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: ti: clkctrl: Fix failed to enable error with double udelay timeout
  clk: ti: dra7-atl-clock: Remove ti_clk_add_alias call
  clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
  clk: sunxi: Fix operator precedence in sunxi_divs_clk_setup
  clk: ast2600: Fix enabling of clocks
  clk: at91: avoid sleeping early
  clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARM
  clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
  clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
  clk: samsung: exynos5433: Fix error paths
  clk: at91: sam9x60: fix programmable clock
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
parents 847120f8 5a60b5aa

drivers/clk/at91/clk-main.c

+4 −1
Original line number Diff line number Diff line
@@ -297,6 +297,9 @@ static int clk_main_probe_frequency(struct regmap *regmap) 
		regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);

		if (mcfr & AT91_PMC_MAINRDY)

			return 0;

		if (system_state < SYSTEM_RUNNING)

			udelay(MAINF_LOOP_MIN_WAIT);

		else

			usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);

	} while (time_before(prep_time, timeout));

drivers/clk/at91/sam9x60.c

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ static const struct clk_pll_characteristics upll_characteristics = { 
};



static const struct clk_programmable_layout sam9x60_programmable_layout = {

	.pres_mask = 0xff,

	.pres_shift = 8,

	.css_mask = 0x1f,

	.have_slck_mck = 0,

drivers/clk/at91/sckc.c

+16 −4
Original line number Diff line number Diff line
@@ -76,6 +76,9 @@ static int clk_slow_osc_prepare(struct clk_hw *hw) 


	writel(tmp | osc->bits->cr_osc32en, sckcr);



	if (system_state < SYSTEM_RUNNING)

		udelay(osc->startup_usec);

	else

		usleep_range(osc->startup_usec, osc->startup_usec + 1);



	return 0;
@@ -187,6 +190,9 @@ static int clk_slow_rc_osc_prepare(struct clk_hw *hw) 


	writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);



	if (system_state < SYSTEM_RUNNING)

		udelay(osc->startup_usec);

	else

		usleep_range(osc->startup_usec, osc->startup_usec + 1);



	return 0;
@@ -288,6 +294,9 @@ static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) 


	writel(tmp, sckcr);



	if (system_state < SYSTEM_RUNNING)

		udelay(SLOWCK_SW_TIME_USEC);

	else

		usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);



	return 0;
@@ -533,6 +542,9 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) 
		return 0;

	}



	if (system_state < SYSTEM_RUNNING)

		udelay(osc->startup_usec);

	else

		usleep_range(osc->startup_usec, osc->startup_usec + 1);

	osc->prepared = true;

drivers/clk/clk-ast2600.c

+4 −3
Original line number Diff line number Diff line
@@ -266,10 +266,11 @@ static int aspeed_g6_clk_enable(struct clk_hw *hw) 


	/* Enable clock */

	if (gate->flags & CLK_GATE_SET_TO_DISABLE) {

		regmap_write(gate->map, get_clock_reg(gate), clk);

	} else {

		/* Use set to clear register */

		/* Clock is clear to enable, so use set to clear register */

		regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);

	} else {

		/* Clock is set to enable, so use write to set register */

		regmap_write(gate->map, get_clock_reg(gate), clk);

	}



	if (gate->reset_idx >= 0) {

drivers/clk/imx/clk-imx8mm.c

+1 −1
Original line number Diff line number Diff line
@@ -638,7 +638,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) 
					   clks[IMX8MM_CLK_A53_DIV],

					   clks[IMX8MM_CLK_A53_SRC],

					   clks[IMX8MM_ARM_PLL_OUT],

					   clks[IMX8MM_CLK_24M]);

					   clks[IMX8MM_SYS_PLL1_800M]);



	imx_check_clocks(clks, ARRAY_SIZE(clks));

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