Commit d97758e0 authored by Serge Semin's avatar Serge Semin Committed by Vinod Koul
Browse files

dmaengine: Introduce min burst length capability 



Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200723005848.31907-4-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2e7d7421

drivers/dma/dmaengine.c

+1 −0
Original line number Diff line number Diff line
@@ -592,6 +592,7 @@ int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) 
	caps->src_addr_widths = device->src_addr_widths;

	caps->dst_addr_widths = device->dst_addr_widths;

	caps->directions = device->directions;

	caps->min_burst = device->min_burst;

	caps->max_burst = device->max_burst;

	caps->residue_granularity = device->residue_granularity;

	caps->descriptor_reuse = device->descriptor_reuse;

include/linux/dmaengine.h

+4 −0
Original line number Diff line number Diff line
@@ -467,6 +467,7 @@ enum dma_residue_granularity { 
 *	Since the enum dma_transfer_direction is not defined as bit flag for

 *	each type, the dma controller should set BIT(<TYPE>) and same

 *	should be checked by controller as well

 * @min_burst: min burst capability per-transfer

 * @max_burst: max burst capability per-transfer

 * @cmd_pause: true, if pause is supported (i.e. for reading residue or

 *	       for resume later)
@@ -480,6 +481,7 @@ struct dma_slave_caps { 
	u32 src_addr_widths;

	u32 dst_addr_widths;

	u32 directions;

	u32 min_burst;

	u32 max_burst;

	bool cmd_pause;

	bool cmd_resume;
@@ -771,6 +773,7 @@ struct dma_filter { 
 *	Since the enum dma_transfer_direction is not defined as bit flag for

 *	each type, the dma controller should set BIT(<TYPE>) and same

 *	should be checked by controller as well

 * @min_burst: min burst capability per-transfer

 * @max_burst: max burst capability per-transfer

 * @residue_granularity: granularity of the transfer residue reported

 *	by tx_status
@@ -841,6 +844,7 @@ struct dma_device { 
	u32 src_addr_widths;

	u32 dst_addr_widths;

	u32 directions;

	u32 min_burst;

	u32 max_burst;

	bool descriptor_reuse;

	enum dma_residue_granularity residue_granularity;

CRA Git | Maintained and supported by SUSTech CRA and CCSE