Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Nuvoton NPCM7xx timer

Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit

timer counters.

Required properties:

- compatible      : "nuvoton,npcm750-timer" for Poleg NPCM750.

- reg             : Offset and length of the register set for the device.

- interrupts      : Contain the timer interrupt with flags for

                    falling edge.

- clocks          : phandle of timer reference clock (usually a 25 MHz clock).

Example:

timer@f0008000 {

    compatible = "nuvoton,npcm750-timer";

    interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

    reg = <0xf0008000 0x50>;

    clocks = <&clk NPCM7XX_CLK_TIMER>;

};

- interrupts :	Should be the clock event device interrupt.

- clocks :	The clocks provided by the SoC to drive the timer, must contain

		an entry for each entry in clock-names.

- clock-names : Must include the following entries: "igp" and "per".

- clock-names : Must include the following entries: "ipg" and "per".

Example:

tpm5: tpm@40260000 {

	help

	  Enables support for the VT8500 driver.

config NPCM7XX_TIMER

	bool "NPCM7xx timer driver" if COMPILE_TEST

	depends on HAS_IOMEM

	select CLKSRC_MMIO

	help

	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,

	  While TIMER0 serves as clockevent and TIMER1 serves as clocksource.

config CADENCE_TTC_TIMER

	bool "Cadence TTC timer driver" if COMPILE_TEST

	depends on COMMON_CLK

obj-$(CONFIG_OXNAS_RPS_TIMER)	+= timer-oxnas-rps.o

obj-$(CONFIG_OWL_TIMER)		+= owl-timer.o

obj-$(CONFIG_SPRD_TIMER)	+= timer-sprd.o

obj-$(CONFIG_NPCM7XX_TIMER)	+= timer-npcm7xx.o

obj-$(CONFIG_ARC_TIMERS)		+= arc_timer.o

obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o

#include <linux/of_irq.h>

#include <linux/sched_clock.h>

#define TPM_PARAM			0x4

#define TPM_PARAM_WIDTH_SHIFT		16

#define TPM_PARAM_WIDTH_MASK		(0xff << 16)

#define TPM_SC				0x10

#define TPM_SC_CMOD_INC_PER_CNT		(0x1 << 3)

#define TPM_SC_CMOD_DIV_DEFAULT		0x3

#define TPM_SC_CMOD_DIV_MAX		0x7

#define TPM_SC_TOF_MASK			(0x1 << 7)

#define TPM_CNT				0x14

#define TPM_MOD				0x18

#define TPM_STATUS			0x1c

#define TPM_C0SC_MODE_SHIFT		2

#define TPM_C0SC_MODE_MASK		0x3c

#define TPM_C0SC_MODE_SW_COMPARE	0x4

#define TPM_C0SC_CHF_MASK		(0x1 << 7)

#define TPM_C0V				0x24

static int counter_width;

static int rating;

static void __iomem *timer_base;

static struct clock_event_device clockevent_tpm;

	tpm_delay_timer.freq = rate;

	register_current_timer_delay(&tpm_delay_timer);

	sched_clock_register(tpm_read_sched_clock, 32, rate);

	sched_clock_register(tpm_read_sched_clock, counter_width, rate);

	return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",

				     rate, 200, 32, clocksource_mmio_readl_up);

				     rate, rating, counter_width,

				     clocksource_mmio_readl_up);

}

static int tpm_set_next_event(unsigned long delta,

	.set_state_oneshot	= tpm_set_state_oneshot,

	.set_next_event		= tpm_set_next_event,

	.set_state_shutdown	= tpm_set_state_shutdown,

	.rating			= 200,

};

static int __init tpm_clockevent_init(unsigned long rate, int irq)

	ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,

			  "i.MX7ULP TPM Timer", &clockevent_tpm);

	clockevent_tpm.rating = rating;

	clockevent_tpm.cpumask = cpumask_of(0);

	clockevent_tpm.irq = irq;

	clockevents_config_and_register(&clockevent_tpm,

					rate, 300, 0xfffffffe);

	clockevents_config_and_register(&clockevent_tpm, rate, 300,

					GENMASK(counter_width - 1, 1));

	return ret;

}

	ipg = of_clk_get_by_name(np, "ipg");

	per = of_clk_get_by_name(np, "per");

	if (IS_ERR(ipg) || IS_ERR(per)) {

		pr_err("tpm: failed to get igp or per clk\n");

		pr_err("tpm: failed to get ipg or per clk\n");

		ret = -ENODEV;

		goto err_clk_get;

	}

		goto err_per_clk_enable;

	}

	counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK)

		>> TPM_PARAM_WIDTH_SHIFT;

	/* use rating 200 for 32-bit counter and 150 for 16-bit counter */

	rating = counter_width == 0x20 ? 200 : 150;

	/*

	 * Initialize tpm module to a known state

	 * 1) Counter disabled

	 * 4) Channel0 disabled

	 * 5) DMA transfers disabled

	 */

	/* make sure counter is disabled */

	writel(0, timer_base + TPM_SC);

	/* TOF is W1C */

	writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);

	writel(0, timer_base + TPM_CNT);

	writel(0, timer_base + TPM_C0SC);

	/* CHF is W1C */

	writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);

	/* increase per cnt, div 8 by default */

	writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,

	/*

	 * increase per cnt,

	 * div 8 for 32-bit counter and div 128 for 16-bit counter

	 */

	writel(TPM_SC_CMOD_INC_PER_CNT |

		(counter_width == 0x20 ?

		TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),

		     timer_base + TPM_SC);

	/* set MOD register to maximum for free running mode */

	writel(0xffffffff, timer_base + TPM_MOD);

	writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);

	rate = clk_get_rate(per) >> 3;

	ret = tpm_clocksource_init(rate);