Commit d932f37c authored Sep 13, 2016 by Rex Zhu Committed by Alex Deucher Sep 16, 2016

drm/amdgpu: not set cg for vce/uvd in late init.



no need to set cg for uvd/vce in late init.
As when ring test, uvd/vce's dpm will be enabled/disabled.
the cg will be set.

fix issue suspend when play video or encode, then resume back,
the clock will be bypassed on Polaris/Fiji.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent aa0ef3cc

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -1367,6 +1367,9 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
		for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_block_status[i].valid)
		continue;
		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_UVD \|\|
		adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_VCE)
		continue;
		/* enable clockgating to save power */
		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
		AMD_CG_STATE_GATE);

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