Commit d92cb162 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: add new helper functions in hwmgr.h 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent be49be40

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+39 −3
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, 
 * reached the given value.The indirect space is described by giving

 * the memory-mapped index of the indirect index register.

 */

void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,

int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,

				uint32_t indirect_port,

				uint32_t index,

				uint32_t value,
@@ -459,14 +459,50 @@ void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, 
{

	if (hwmgr == NULL || hwmgr->device == NULL) {

		pr_err("Invalid Hardware Manager!");

		return;

		return -EINVAL;

	}



	cgs_write_register(hwmgr->device, indirect_port, index);

	phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);

	return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);

}



int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,

					uint32_t index,

					uint32_t value, uint32_t mask)

{

	uint32_t i;

	uint32_t cur_value;



	if (hwmgr == NULL || hwmgr->device == NULL)

		return -EINVAL;



	for (i = 0; i < hwmgr->usec_timeout; i++) {

		cur_value = cgs_read_register(hwmgr->device,

									index);

		if ((cur_value & mask) != (value & mask))

			break;

		udelay(1);

	}



	/* timeout means wrong logic */

	if (i == hwmgr->usec_timeout)

		return -ETIME;

	return 0;

}



int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,

						uint32_t indirect_port,

						uint32_t index,

						uint32_t value,

						uint32_t mask)

{

	if (hwmgr == NULL || hwmgr->device == NULL)

		return -EINVAL;



	cgs_write_register(hwmgr->device, indirect_port, index);

	return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,

						value, mask);

}



bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)

{

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+8 −2
Original line number Diff line number Diff line
@@ -792,12 +792,19 @@ extern int hwmgr_handle_task(struct pp_instance *handle, 
extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,

				uint32_t value, uint32_t mask);



extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,

extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,

				uint32_t indirect_port,

				uint32_t index,

				uint32_t value,

				uint32_t mask);



extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,

					uint32_t index,

					uint32_t value, uint32_t mask);

extern int phm_wait_for_indirect_register_unequal(

				struct pp_hwmgr *hwmgr,

				uint32_t indirect_port, uint32_t index,

				uint32_t value, uint32_t mask);





extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
@@ -882,5 +889,4 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t 
	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\

			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))





#endif /* _HWMGR_H_ */

drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr) 
	reg = soc15_get_register_offset(MP1_HWID, 0,

			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);



	smum_wait_for_register_unequal(hwmgr, reg,

	phm_wait_for_register_unequal(hwmgr, reg,

			0, MP1_C2PMSG_90__CONTENT_MASK);



	return cgs_read_register(hwmgr->device, reg);

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

+1 −2
Original line number Diff line number Diff line
@@ -487,11 +487,10 @@ int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) 
	uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);

	uint32_t ret;



	ret = smum_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,

	ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,

					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, UcodeLoadStatus),

					fw_mask, fw_mask);



	return ret;

}

drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c

+1 −1
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr) 
	reg = soc15_get_register_offset(MP1_HWID, 0,

			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);



	smum_wait_for_register_unequal(hwmgr, reg,

	phm_wait_for_register_unequal(hwmgr, reg,

			0, MP1_C2PMSG_90__CONTENT_MASK);



	return cgs_read_register(hwmgr->device, reg);

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