habanalabs: add sysfs and hwmon support (d91389bc) · Commits · 戴 / test

Documentation/ABI/testing/sysfs-driver-habanalabs

0 → 100644

+190 −0

Original line number	Diff line number	Diff line
		What: /sys/class/habanalabs/hl<n>/armcp_kernel_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the Linux kernel running on the device's CPU

		What: /sys/class/habanalabs/hl<n>/armcp_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the application running on the device's CPU

		What: /sys/class/habanalabs/hl<n>/cpld_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the Device's CPLD F/W

		What: /sys/class/habanalabs/hl<n>/device_type
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the code name of the device according to its type.
		The supported values are: "GOYA"

		What: /sys/class/habanalabs/hl<n>/eeprom
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: A binary file attribute that contains the contents of the
		on-board EEPROM

		What: /sys/class/habanalabs/hl<n>/fuse_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the device's version from the eFuse

		What: /sys/class/habanalabs/hl<n>/hard_reset
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Interface to trigger a hard-reset operation for the device.
		Hard-reset will reset ALL internal components of the device
		except for the PCI interface and the internal PLLs

		What: /sys/class/habanalabs/hl<n>/hard_reset_cnt
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays how many times the device have undergone a hard-reset
		operation since the driver was loaded

		What: /sys/class/habanalabs/hl<n>/high_pll
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Allows the user to set the maximum clock frequency for MME, TPC
		and IC when the power management profile is set to "automatic".

		What: /sys/class/habanalabs/hl<n>/ic_clk
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Allows the user to set the maximum clock frequency of the
		Interconnect fabric. Writes to this parameter affect the device
		only when the power management profile is set to "manual" mode.
		The device IC clock might be set to lower value then the
		maximum. The user should read the ic_clk_curr to see the actual
		frequency value of the IC

		What: /sys/class/habanalabs/hl<n>/ic_clk_curr
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the current clock frequency of the Interconnect fabric

		What: /sys/class/habanalabs/hl<n>/infineon_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the Device's power supply F/W code

		What: /sys/class/habanalabs/hl<n>/max_power
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Allows the user to set the maximum power consumption of the
		device in milliwatts.

		What: /sys/class/habanalabs/hl<n>/mme_clk
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Allows the user to set the maximum clock frequency of the
		MME compute engine. Writes to this parameter affect the device
		only when the power management profile is set to "manual" mode.
		The device MME clock might be set to lower value then the
		maximum. The user should read the mme_clk_curr to see the actual
		frequency value of the MME

		What: /sys/class/habanalabs/hl<n>/mme_clk_curr
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the current clock frequency of the MME compute engine

		What: /sys/class/habanalabs/hl<n>/pci_addr
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the PCI address of the device. This is needed so the
		user would be able to open a device based on its PCI address

		What: /sys/class/habanalabs/hl<n>/pm_mng_profile
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Power management profile. Values are "auto", "manual". In "auto"
		mode, the driver will set the maximum clock frequency to a high
		value when a user-space process opens the device's file (unless
		it was already opened by another process). The driver will set
		the max clock frequency to a low value when there are no user
		processes that are opened on the device's file. In "manual"
		mode, the user sets the maximum clock frequency by writing to
		ic_clk, mme_clk and tpc_clk


		What: /sys/class/habanalabs/hl<n>/preboot_btl_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the device's preboot F/W code

		What: /sys/class/habanalabs/hl<n>/soft_reset
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Interface to trigger a soft-reset operation for the device.
		Soft-reset will reset only the compute and DMA engines of the
		device

		What: /sys/class/habanalabs/hl<n>/soft_reset_cnt
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays how many times the device have undergone a soft-reset
		operation since the driver was loaded

		What: /sys/class/habanalabs/hl<n>/status
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Status of the card: "Operational", "Malfunction", "In reset".

		What: /sys/class/habanalabs/hl<n>/thermal_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the Device's thermal daemon

		What: /sys/class/habanalabs/hl<n>/tpc_clk
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Allows the user to set the maximum clock frequency of the
		TPC compute engines. Writes to this parameter affect the device
		only when the power management profile is set to "manual" mode.
		The device TPC clock might be set to lower value then the
		maximum. The user should read the tpc_clk_curr to see the actual
		frequency value of the TPC

		What: /sys/class/habanalabs/hl<n>/tpc_clk_curr
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the current clock frequency of the TPC compute engines

		What: /sys/class/habanalabs/hl<n>/uboot_ver
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Version of the u-boot running on the device's CPU

		What: /sys/class/habanalabs/hl<n>/write_open_cnt
		Date: Jan 2019
		KernelVersion: 5.1
		Contact: oded.gabbay@gmail.com
		Description: Displays the total number of user processes that are currently
		opened on the device's file

drivers/misc/habanalabs/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -5,7 +5,7 @@
		obj-m := habanalabs.o

		habanalabs-y := habanalabs_drv.o device.o context.o asid.o habanalabs_ioctl.o \
		command_buffer.o hw_queue.o irq.o
		command_buffer.o hw_queue.o irq.o sysfs.o hwmon.o

		include $(src)/goya/Makefile
		habanalabs-y += $(HL_GOYA_FILES)

drivers/misc/habanalabs/device.c

+163 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,7 @@

		#include <linux/pci.h>
		#include <linux/delay.h>
		#include <linux/hwmon.h>

		static void hpriv_release(struct kref *ref)
		{
		@@ -188,6 +189,13 @@ static int device_early_init(struct hl_device *hdev)
		goto free_cq_wq;
		}

		hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info),
		GFP_KERNEL);
		if (!hdev->hl_chip_info) {
		rc = -ENOMEM;
		goto free_eq_wq;
		}

		hl_cb_mgr_init(&hdev->kernel_cb_mgr);

		mutex_init(&hdev->fd_open_cnt_lock);
		@@ -196,6 +204,8 @@ static int device_early_init(struct hl_device *hdev)

		return 0;

		free_eq_wq:
		destroy_workqueue(hdev->eq_wq);
		free_cq_wq:
		destroy_workqueue(hdev->cq_wq);
		asid_fini:
		@@ -219,6 +229,8 @@ static void device_early_fini(struct hl_device *hdev)

		hl_cb_mgr_fini(hdev, &hdev->kernel_cb_mgr);

		kfree(hdev->hl_chip_info);

		destroy_workqueue(hdev->eq_wq);
		destroy_workqueue(hdev->cq_wq);

		@@ -230,6 +242,118 @@ static void device_early_fini(struct hl_device *hdev)
		mutex_destroy(&hdev->fd_open_cnt_lock);
		}

		static void set_freq_to_low_job(struct work_struct *work)
		{
		struct hl_device *hdev = container_of(work, struct hl_device,
		work_freq.work);

		if (atomic_read(&hdev->fd_open_cnt) == 0)
		hl_device_set_frequency(hdev, PLL_LOW);

		schedule_delayed_work(&hdev->work_freq,
		usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
		}

		/*
		* device_late_init - do late stuff initialization for the habanalabs device
		*
		* @hdev: pointer to habanalabs device structure
		*
		* Do stuff that either needs the device H/W queues to be active or needs
		* to happen after all the rest of the initialization is finished
		*/
		static int device_late_init(struct hl_device *hdev)
		{
		int rc;

		INIT_DELAYED_WORK(&hdev->work_freq, set_freq_to_low_job);
		hdev->high_pll = hdev->asic_prop.high_pll;

		/* force setting to low frequency */
		atomic_set(&hdev->curr_pll_profile, PLL_LOW);

		if (hdev->pm_mng_profile == PM_AUTO)
		hdev->asic_funcs->set_pll_profile(hdev, PLL_LOW);
		else
		hdev->asic_funcs->set_pll_profile(hdev, PLL_LAST);

		if (hdev->asic_funcs->late_init) {
		rc = hdev->asic_funcs->late_init(hdev);
		if (rc) {
		dev_err(hdev->dev,
		"failed late initialization for the H/W\n");
		return rc;
		}
		}

		schedule_delayed_work(&hdev->work_freq,
		usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));

		hdev->late_init_done = true;

		return 0;
		}

		/*
		* device_late_fini - finalize all that was done in device_late_init
		*
		* @hdev: pointer to habanalabs device structure
		*
		*/
		static void device_late_fini(struct hl_device *hdev)
		{
		if (!hdev->late_init_done)
		return;

		cancel_delayed_work_sync(&hdev->work_freq);

		if (hdev->asic_funcs->late_fini)
		hdev->asic_funcs->late_fini(hdev);

		hdev->late_init_done = false;
		}

		/*
		* hl_device_set_frequency - set the frequency of the device
		*
		* @hdev: pointer to habanalabs device structure
		* @freq: the new frequency value
		*
		* Change the frequency if needed.
		* We allose to set PLL to low only if there is no user process
		* Returns 0 if no change was done, otherwise returns 1;
		*/
		int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
		{
		enum hl_pll_frequency old_freq =
		(freq == PLL_HIGH) ? PLL_LOW : PLL_HIGH;
		int ret;

		if (hdev->pm_mng_profile == PM_MANUAL)
		return 0;

		ret = atomic_cmpxchg(&hdev->curr_pll_profile, old_freq, freq);
		if (ret == freq)
		return 0;

		/*
		* in case we want to lower frequency, check if device is not
		* opened. We must have a check here to workaround race condition with
		* hl_device_open
		*/
		if ((freq == PLL_LOW) && (atomic_read(&hdev->fd_open_cnt) > 0)) {
		atomic_set(&hdev->curr_pll_profile, PLL_HIGH);
		return 0;
		}

		dev_dbg(hdev->dev, "Changing device frequency to %s\n",
		freq == PLL_HIGH ? "high" : "low");

		hdev->asic_funcs->set_pll_profile(hdev, freq);

		return 1;
		}

		/*
		* hl_device_suspend - initiate device suspend
		*
		@@ -390,6 +514,12 @@ int hl_device_init(struct hl_device hdev, struct class hclass)
		goto release_ctx;
		}

		rc = hl_sysfs_init(hdev);
		if (rc) {
		dev_err(hdev->dev, "failed to initialize sysfs\n");
		goto free_cb_pool;
		}

		rc = hdev->asic_funcs->hw_init(hdev);
		if (rc) {
		dev_err(hdev->dev, "failed to initialize the H/W\n");
		@@ -407,11 +537,38 @@ int hl_device_init(struct hl_device hdev, struct class hclass)
		goto out_disabled;
		}

		/* After test_queues, KMD can start sending messages to device CPU */

		rc = device_late_init(hdev);
		if (rc) {
		dev_err(hdev->dev, "Failed late initialization\n");
		rc = 0;
		goto out_disabled;
		}

		dev_info(hdev->dev, "Found %s device with %lluGB DRAM\n",
		hdev->asic_name,
		hdev->asic_prop.dram_size / 1024 / 1024 / 1024);

		/*
		* hl_hwmon_init must be called after device_late_init, because only
		* there we get the information from the device about which
		* hwmon-related sensors the device supports
		*/
		rc = hl_hwmon_init(hdev);
		if (rc) {
		dev_err(hdev->dev, "Failed to initialize hwmon\n");
		rc = 0;
		goto out_disabled;
		}

		dev_notice(hdev->dev,
		"Successfully added device to habanalabs driver\n");

		return 0;

		free_cb_pool:
		hl_cb_pool_fini(hdev);
		release_ctx:
		if (hl_ctx_put(hdev->kernel_ctx) != 1)
		dev_err(hdev->dev,
		@@ -461,6 +618,12 @@ void hl_device_fini(struct hl_device *hdev)
		/* Mark device as disabled */
		hdev->disabled = true;

		hl_hwmon_fini(hdev);

		device_late_fini(hdev);

		hl_sysfs_fini(hdev);

		/*
		* Halt the engines and disable interrupts so we won't get any more
		* completions from H/W and we won't have any accesses from the

drivers/misc/habanalabs/goya/Makefile

+1 −1

Original line number	Diff line number	Diff line
		subdir-ccflags-y += -I$(src)

		HL_GOYA_FILES := goya/goya.o goya/goya_security.o
		HL_GOYA_FILES := goya/goya.o goya/goya_security.o goya/goya_hwmgr.o

drivers/misc/habanalabs/goya/goya.c

+230 −0

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@
		#include <linux/pci.h>
		#include <linux/genalloc.h>
		#include <linux/firmware.h>
		#include <linux/hwmon.h>
		#include <linux/io-64-nonatomic-lo-hi.h>
		#include <linux/io-64-nonatomic-hi-lo.h>

		@@ -119,6 +120,8 @@ static const char *goya_axi_name[GOYA_MAX_INITIATORS] = {

		#define GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE 121

		static int goya_armcp_info_get(struct hl_device *hdev);

		static void goya_get_fixed_properties(struct hl_device *hdev)
		{
		struct asic_fixed_properties *prop = &hdev->asic_prop;
		@@ -166,6 +169,7 @@ static void goya_get_fixed_properties(struct hl_device *hdev)
		prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
		prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
		prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
		prop->max_power_default = MAX_POWER_DEFAULT;
		prop->tpc_enabled_mask = TPC_ENABLED_MASK;

		prop->high_pll = PLL_HIGH_DEFAULT;
		@@ -559,6 +563,89 @@ int goya_early_fini(struct hl_device *hdev)
		return 0;
		}

		/*
		* goya_fetch_psoc_frequency - Fetch PSOC frequency values
		*
		* @hdev: pointer to hl_device structure
		*
		*/
		static void goya_fetch_psoc_frequency(struct hl_device *hdev)
		{
		struct asic_fixed_properties *prop = &hdev->asic_prop;

		prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
		prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
		prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
		prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
		}

		/*
		* goya_late_init - GOYA late initialization code
		*
		* @hdev: pointer to hl_device structure
		*
		* Get ArmCP info and send message to CPU to enable PCI access
		*/
		static int goya_late_init(struct hl_device *hdev)
		{
		struct asic_fixed_properties *prop = &hdev->asic_prop;
		struct goya_device *goya = hdev->asic_specific;
		int rc;

		rc = goya->armcp_info_get(hdev);
		if (rc) {
		dev_err(hdev->dev, "Failed to get armcp info\n");
		return rc;
		}

		/* Now that we have the DRAM size in ASIC prop, we need to check
		* its size and configure the DMA_IF DDR wrap protection (which is in
		* the MMU block) accordingly. The value is the log2 of the DRAM size
		*/
		WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));

		rc = goya_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
		if (rc) {
		dev_err(hdev->dev, "Failed to enable PCI access from CPU\n");
		return rc;
		}

		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
		GOYA_ASYNC_EVENT_ID_INTS_REGISTER);

		goya_fetch_psoc_frequency(hdev);

		return 0;
		}

		/*
		* goya_late_fini - GOYA late tear-down code
		*
		* @hdev: pointer to hl_device structure
		*
		* Free sensors allocated structures
		*/
		void goya_late_fini(struct hl_device *hdev)
		{
		const struct hwmon_channel_info **channel_info_arr;
		int i = 0;

		if (!hdev->hl_chip_info->info)
		return;

		channel_info_arr = hdev->hl_chip_info->info;

		while (channel_info_arr[i]) {
		kfree(channel_info_arr[i]->config);
		kfree(channel_info_arr[i]);
		i++;
		}

		kfree(channel_info_arr);

		hdev->hl_chip_info->info = NULL;
		}

		/*
		* goya_sw_init - Goya software initialization code
		*
		@@ -576,9 +663,15 @@ static int goya_sw_init(struct hl_device *hdev)
		return -ENOMEM;

		goya->test_cpu_queue = goya_test_cpu_queue;
		goya->armcp_info_get = goya_armcp_info_get;

		/* according to goya_init_iatu */
		goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;

		goya->mme_clk = GOYA_PLL_FREQ_LOW;
		goya->tpc_clk = GOYA_PLL_FREQ_LOW;
		goya->ic_clk = GOYA_PLL_FREQ_LOW;

		hdev->asic_specific = goya;

		/* Create DMA pool for small allocations */
		@@ -3217,6 +3310,87 @@ void goya_get_events_stat(struct hl_device hdev, u32 *size)
		return goya->events_stat;
		}

		static int goya_armcp_info_get(struct hl_device *hdev)
		{
		struct goya_device *goya = hdev->asic_specific;
		struct asic_fixed_properties *prop = &hdev->asic_prop;
		struct armcp_packet pkt;
		void *armcp_info_cpu_addr;
		dma_addr_t armcp_info_dma_addr;
		u64 dram_size;
		long result;
		int rc;

		if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
		return 0;

		armcp_info_cpu_addr =
		hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
		sizeof(struct armcp_info), &armcp_info_dma_addr);
		if (!armcp_info_cpu_addr) {
		dev_err(hdev->dev,
		"Failed to allocate DMA memory for ArmCP info packet\n");
		return -ENOMEM;
		}

		memset(armcp_info_cpu_addr, 0, sizeof(struct armcp_info));

		memset(&pkt, 0, sizeof(pkt));

		pkt.ctl = ARMCP_PACKET_INFO_GET << ARMCP_PKT_CTL_OPCODE_SHIFT;
		pkt.addr = armcp_info_dma_addr + prop->host_phys_base_address;
		pkt.data_max_size = sizeof(struct armcp_info);

		rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
		GOYA_ARMCP_INFO_TIMEOUT, &result);

		if (rc) {
		dev_err(hdev->dev,
		"Failed to send armcp info pkt, error %d\n", rc);
		goto out;
		}

		memcpy(&prop->armcp_info, armcp_info_cpu_addr,
		sizeof(prop->armcp_info));

		dram_size = prop->armcp_info.dram_size;
		if (dram_size) {
		if ((!is_power_of_2(dram_size)) \|\|
		(dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
		dev_err(hdev->dev,
		"F/W reported invalid DRAM size %llu. Trying to use default size\n",
		dram_size);
		dram_size = DRAM_PHYS_DEFAULT_SIZE;
		}

		prop->dram_size = dram_size;
		prop->dram_end_address = prop->dram_base_address + dram_size;
		}

		rc = hl_build_hwmon_channel_info(hdev, prop->armcp_info.sensors);
		if (rc) {
		dev_err(hdev->dev,
		"Failed to build hwmon channel info, error %d\n", rc);
		rc = -EFAULT;
		goto out;
		}

		out:
		hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev,
		sizeof(struct armcp_info), armcp_info_cpu_addr);

		return rc;
		}

		static void goya_init_clock_gating(struct hl_device *hdev)
		{

		}

		static void goya_disable_clock_gating(struct hl_device *hdev)
		{

		}

		static void goya_hw_queues_lock(struct hl_device *hdev)
		{
		@@ -3232,9 +3406,60 @@ static void goya_hw_queues_unlock(struct hl_device *hdev)
		spin_unlock(&goya->hw_queues_lock);
		}

		int goya_get_eeprom_data(struct hl_device hdev, void data, size_t max_size)
		{
		struct goya_device *goya = hdev->asic_specific;
		struct asic_fixed_properties *prop = &hdev->asic_prop;
		struct armcp_packet pkt;
		void *eeprom_info_cpu_addr;
		dma_addr_t eeprom_info_dma_addr;
		long result;
		int rc;

		if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
		return 0;

		eeprom_info_cpu_addr =
		hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev,
		max_size, &eeprom_info_dma_addr);
		if (!eeprom_info_cpu_addr) {
		dev_err(hdev->dev,
		"Failed to allocate DMA memory for EEPROM info packet\n");
		return -ENOMEM;
		}

		memset(eeprom_info_cpu_addr, 0, max_size);

		memset(&pkt, 0, sizeof(pkt));

		pkt.ctl = ARMCP_PACKET_EEPROM_DATA_GET << ARMCP_PKT_CTL_OPCODE_SHIFT;
		pkt.addr = eeprom_info_dma_addr + prop->host_phys_base_address;
		pkt.data_max_size = max_size;

		rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
		GOYA_ARMCP_EEPROM_TIMEOUT, &result);

		if (rc) {
		dev_err(hdev->dev,
		"Failed to send armcp EEPROM pkt, error %d\n", rc);
		goto out;
		}

		/* result contains the actual size */
		memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size));

		out:
		hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, max_size,
		eeprom_info_cpu_addr);

		return rc;
		}

		static const struct hl_asic_funcs goya_funcs = {
		.early_init = goya_early_init,
		.early_fini = goya_early_fini,
		.late_init = goya_late_init,
		.late_fini = goya_late_fini,
		.sw_init = goya_sw_init,
		.sw_fini = goya_sw_fini,
		.hw_init = goya_hw_init,
		@@ -3255,10 +3480,15 @@ static const struct hl_asic_funcs goya_funcs = {
		.cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
		.cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
		.update_eq_ci = goya_update_eq_ci,
		.add_device_attr = goya_add_device_attr,
		.handle_eqe = goya_handle_eqe,
		.set_pll_profile = goya_set_pll_profile,
		.get_events_stat = goya_get_events_stat,
		.enable_clock_gating = goya_init_clock_gating,
		.disable_clock_gating = goya_disable_clock_gating,
		.hw_queues_lock = goya_hw_queues_lock,
		.hw_queues_unlock = goya_hw_queues_unlock,
		.get_eeprom_data = goya_get_eeprom_data,
		.send_cpu_message = goya_send_cpu_message
		};

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