Commit d90c76bb authored Mar 08, 2018 by Eddie James Committed by Stephen Boyd Mar 15, 2018

clk: aspeed: Fix is_enabled for certain clocks



Some of the Aspeed clocks are disabled by setting the relevant bit in
the "clock stop control" register to one, while others are disabled by
setting their bit to zero. The driver already uses a flag per gate  to
identify this behavior, but doesn't apply it in the clock is_enabled
function.

Use the existing gate flag to correctly return whether or not a clock
is enabled in the aspeed_clk_is_enabled function.

Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Fixes: 6671507f ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 55c19eee

drivers/clk/clk-aspeed.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -259,11 +259,12 @@ static int aspeed_clk_is_enabled(struct clk_hw *hw)
		{
		struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
		u32 clk = BIT(gate->clock_idx);
		u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
		u32 reg;

		regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);

		return (reg & clk) ? 0 : 1;
		return ((reg & clk) == enval) ? 1 : 0;
		}

		static const struct clk_ops aspeed_clk_gate_ops = {

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