Commit d8f4a9ed authored by Thierry Reding's avatar Thierry Reding Committed by Dave Airlie
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drm: Add NVIDIA Tegra20 support 



This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.

Signed-off-by: default avatarThierry Reding <thierry.reding@avionic-design.de>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarMark Zhang <markz@nvidia.com>
Reviewed-by: default avatarMark Zhang <markz@nvidia.com>
Tested-by: default avatarMark Zhang <markz@nvidia.com>
Tested-and-acked-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Acked-by: default avatarTerje Bergstrom <tbergstrom@nvidia.com>
Tested-by: default avatarTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent b27b6d32

Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

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NVIDIA Tegra host1x



Required properties:

- compatible: "nvidia,tegra<chip>-host1x"

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt outputs from the controller.

- #address-cells: The number of cells used to represent physical base addresses

  in the host1x address space. Should be 1.

- #size-cells: The number of cells used to represent the size of an address

  range in the host1x address space. Should be 1.

- ranges: The mapping of the host1x address space to the CPU address space.



The host1x top-level node defines a number of children, each representing one

of the following host1x client modules:



- mpe: video encoder



  Required properties:

  - compatible: "nvidia,tegra<chip>-mpe"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- vi: video input



  Required properties:

  - compatible: "nvidia,tegra<chip>-vi"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- epp: encoder pre-processor



  Required properties:

  - compatible: "nvidia,tegra<chip>-epp"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- isp: image signal processor



  Required properties:

  - compatible: "nvidia,tegra<chip>-isp"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- gr2d: 2D graphics engine



  Required properties:

  - compatible: "nvidia,tegra<chip>-gr2d"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- gr3d: 3D graphics engine



  Required properties:

  - compatible: "nvidia,tegra<chip>-gr3d"

  - reg: Physical base address and length of the controller's registers.



- dc: display controller



  Required properties:

  - compatible: "nvidia,tegra<chip>-dc"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



  Each display controller node has a child node, named "rgb", that represents

  the RGB output associated with the controller. It can take the following

  optional properties:

  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection

  - nvidia,edid: supplies a binary EDID blob



- hdmi: High Definition Multimedia Interface



  Required properties:

  - compatible: "nvidia,tegra<chip>-hdmi"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - vdd-supply: regulator for supply voltage

  - pll-supply: regulator for PLL



  Optional properties:

  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection

  - nvidia,edid: supplies a binary EDID blob



- tvo: TV encoder output



  Required properties:

  - compatible: "nvidia,tegra<chip>-tvo"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.



- dsi: display serial interface



  Required properties:

  - compatible: "nvidia,tegra<chip>-dsi"

  - reg: Physical base address and length of the controller's registers.



Example:



/ {

	...



	host1x {

		compatible = "nvidia,tegra20-host1x", "simple-bus";

		reg = <0x50000000 0x00024000>;

		interrupts = <0 65 0x04   /* mpcore syncpt */

			      0 67 0x04>; /* mpcore general */



		#address-cells = <1>;

		#size-cells = <1>;



		ranges = <0x54000000 0x54000000 0x04000000>;



		mpe {

			compatible = "nvidia,tegra20-mpe";

			reg = <0x54040000 0x00040000>;

			interrupts = <0 68 0x04>;

		};



		vi {

			compatible = "nvidia,tegra20-vi";

			reg = <0x54080000 0x00040000>;

			interrupts = <0 69 0x04>;

		};



		epp {

			compatible = "nvidia,tegra20-epp";

			reg = <0x540c0000 0x00040000>;

			interrupts = <0 70 0x04>;

		};



		isp {

			compatible = "nvidia,tegra20-isp";

			reg = <0x54100000 0x00040000>;

			interrupts = <0 71 0x04>;

		};



		gr2d {

			compatible = "nvidia,tegra20-gr2d";

			reg = <0x54140000 0x00040000>;

			interrupts = <0 72 0x04>;

		};



		gr3d {

			compatible = "nvidia,tegra20-gr3d";

			reg = <0x54180000 0x00040000>;

		};



		dc@54200000 {

			compatible = "nvidia,tegra20-dc";

			reg = <0x54200000 0x00040000>;

			interrupts = <0 73 0x04>;



			rgb {

				status = "disabled";

			};

		};



		dc@54240000 {

			compatible = "nvidia,tegra20-dc";

			reg = <0x54240000 0x00040000>;

			interrupts = <0 74 0x04>;



			rgb {

				status = "disabled";

			};

		};



		hdmi {

			compatible = "nvidia,tegra20-hdmi";

			reg = <0x54280000 0x00040000>;

			interrupts = <0 75 0x04>;

			status = "disabled";

		};



		tvo {

			compatible = "nvidia,tegra20-tvo";

			reg = <0x542c0000 0x00040000>;

			interrupts = <0 76 0x04>;

			status = "disabled";

		};



		dsi {

			compatible = "nvidia,tegra20-dsi";

			reg = <0x54300000 0x00040000>;

			status = "disabled";

		};

	};



	...

};

drivers/gpu/drm/Kconfig

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@@ -210,3 +210,5 @@ source "drivers/gpu/drm/mgag200/Kconfig" 
source "drivers/gpu/drm/cirrus/Kconfig"



source "drivers/gpu/drm/shmobile/Kconfig"



source "drivers/gpu/drm/tegra/Kconfig"

drivers/gpu/drm/Makefile

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@@ -48,4 +48,5 @@ obj-$(CONFIG_DRM_GMA500) += gma500/ 
obj-$(CONFIG_DRM_UDL) += udl/

obj-$(CONFIG_DRM_AST) += ast/

obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/

obj-$(CONFIG_DRM_TEGRA) += tegra/

obj-y			+= i2c/

drivers/gpu/drm/tegra/Kconfig

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config DRM_TEGRA

	tristate "NVIDIA Tegra DRM"

	depends on DRM && OF && ARCH_TEGRA

	select DRM_KMS_HELPER

	select DRM_GEM_CMA_HELPER

	select DRM_KMS_CMA_HELPER

	select FB_CFB_FILLRECT

	select FB_CFB_COPYAREA

	select FB_CFB_IMAGEBLIT

	help

	  Choose this option if you have an NVIDIA Tegra SoC.



	  To compile this driver as a module, choose M here: the module

	  will be called tegra-drm.



if DRM_TEGRA



config DRM_TEGRA_DEBUG

	bool "NVIDIA Tegra DRM debug support"

	help

	  Say yes here to enable debugging support.



endif

drivers/gpu/drm/tegra/Makefile

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ccflags-y := -Iinclude/drm

ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG



tegra-drm-y := drm.o fb.o dc.o host1x.o

tegra-drm-y += output.o rgb.o



obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o

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