Commit d8eabc37 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/msr-index: Cleanup bit defines 



Greg pointed out that speculation related bit defines are using (1 << N)
format instead of BIT(N). Aside of that (1 << N) is wrong as it should use
1UL at least.

Clean it up.

[ Josh Poimboeuf: Fix tools build ]

Reported-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarFrederic Weisbecker <frederic@kernel.org>
Reviewed-by: default avatarJon Masters <jcm@redhat.com>
Tested-by: default avatarJon Masters <jcm@redhat.com>
parent 1c163f4c

arch/x86/include/asm/msr-index.h

+18 −16
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 
#ifndef _ASM_X86_MSR_INDEX_H

#define _ASM_X86_MSR_INDEX_H



#include <linux/bits.h>



/*

 * CPU model specific register (MSR) numbers.

 *
@@ -40,14 +42,14 @@ 
/* Intel MSRs. Some also available on other CPUs */



#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */

#define SPEC_CTRL_IBRS			(1 << 0)   /* Indirect Branch Restricted Speculation */

#define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */

#define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */

#define SPEC_CTRL_STIBP			(1 << SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */

#define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */

#define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */

#define SPEC_CTRL_SSBD			(1 << SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */

#define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */



#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */

#define PRED_CMD_IBPB			(1 << 0)   /* Indirect Branch Prediction Barrier */

#define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */



#define MSR_PPIN_CTL			0x0000004e

#define MSR_PPIN			0x0000004f
@@ -69,17 +71,17 @@ 
#define MSR_MTRRcap			0x000000fe



#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a

#define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */

#define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */

#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	(1 << 3)   /* Skip L1D flush on vmentry */

#define ARCH_CAP_SSB_NO			(1 << 4)   /*

#define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */

#define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */

#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */

#define ARCH_CAP_SSB_NO			BIT(4)	/*

						 * Not susceptible to Speculative Store Bypass

						 * attack, so no Speculative Store Bypass

						 * control required.

						 */



#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			(1 << 0)   /*

#define L1D_FLUSH			BIT(0)	/*

						 * Writeback and invalidate the

						 * L1 data cache.

						 */

tools/power/x86/turbostat/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ ifeq ("$(origin O)", "command line") 
endif



turbostat : turbostat.c

override CFLAGS +=	-Wall

override CFLAGS +=	-Wall -I../../../include

override CFLAGS +=	-DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'

override CFLAGS +=	-DINTEL_FAMILY_HEADER='"../../../../arch/x86/include/asm/intel-family.h"'

tools/power/x86/x86_energy_perf_policy/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ ifeq ("$(origin O)", "command line") 
endif



x86_energy_perf_policy : x86_energy_perf_policy.c

override CFLAGS +=	-Wall

override CFLAGS +=	-Wall -I../../../include

override CFLAGS +=	-DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'



%: %.c

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