Commit d8ea757b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa 

Pull Xtensa updates from Max Filippov:
 "Updates for the xtensa architecture.  It is a combined set of patches
  for 4.8 that never got to the mainline and new patches for 4.9.

   - add new kernel memory layouts for MMUv3 cores: with 256MB and 512MB
     KSEG size, starting at physical address other than 0

   - make kernel load address configurable

   - clean up kernel memory layout macros

   - drop sysmem early allocator and switch to memblock

   - enable kmemleak and memory reservation from the device tree

   - wire up new syscalls: userfaultfd, membarrier, mlock2,
     copy_file_range, preadv2 and pwritev2

   - add new platform: Cadence Configurable System Platform (CSP) and
     new core variant for it: xt_lnx

   - rearrange CCOUNT calibration code, make most of it generic

   - improve machine reset code (XTFPGA now reboots reliably with MMUv3
     cores)

   - provide default memmap command line option for configurations
     without device tree support

   - ISS fixes: simdisk is now capable of using highmem pages, panic
     correctly terminates simulator"

* tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa: (24 commits)
  xtensa: disable MMU initialization option on MMUv2 cores
  xtensa: add default memmap and mmio32native options to defconfigs
  xtensa: add default memmap option to common_defconfig
  xtensa: add default memmap option to iss_defconfig
  xtensa: ISS: allow simdisk to use high memory buffers
  xtensa: ISS: define simc_exit and use it instead of inline asm
  xtensa: xtfpga: group platform_* functions together
  xtensa: rearrange CCOUNT calibration
  xtensa: xtfpga: use clock provider, don't update DT
  xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
  xtensa: initialize MMU before jumping to reset vector
  xtensa: fix icountlevel setting in cpu_reset
  xtensa: extract common CPU reset code into separate function
  xtensa: Added Cadence CSP kernel configuration for Xtensa
  xtensa: fix default kernel load address
  xtensa: wire up new syscalls
  xtensa: support reserved-memory DT node
  xtensa: drop sysmem and switch to memblock
  xtensa: minimize use of PLATFORM_DEFAULT_MEM_{ADDR,SIZE}
  xtensa: cleanup MMU setup and kernel layout macros
  ...
parents 41844e36 a4c6be5a

Documentation/xtensa/mmu.txt

+146 −27
Original line number Diff line number Diff line
@@ -3,15 +3,8 @@ MMUv3 initialization sequence. 
The code in the initialize_mmu macro sets up MMUv3 memory mapping

identically to MMUv2 fixed memory mapping. Depending on

CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is

located in one of the following address ranges:



    0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout;

    			 typically ROM)

    0x00000000..0x07FFFFFF (system RAM; this code is actually linked

    			 at 0xD0000000..0xD7FFFFFF [cached]

    			 or 0xD8000000..0xDFFFFFFF [uncached];

    			 in any case, initially runs elsewhere

    			 than linked, so have to be careful)

located in addresses it was linked for (symbol undefined), or not

(symbol defined), so it needs to be position-independent.



The code has the following assumptions:

  This code fragment is run only on an MMU v3.
@@ -28,24 +21,26 @@ TLB setup proceeds along the following steps. 
    PA = physical address (two upper nibbles of it);

    pc = physical range that contains this code;



After step 2, we jump to virtual address in 0x40000000..0x5fffffff

that corresponds to next instruction to execute in this code.

After step 4, we jump to intended (linked) address of this code.

After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff

or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below

0x40000000 or above. That address corresponds to next instruction to execute

in this code. After step 4, we jump to intended (linked) address of this code.

The scheme below assumes that the kernel is loaded below 0x40000000.



        Step0  Step1  Step2  Step3          Step4  Step5

 ============  =====  ============  =====  ============  =====

   VA      PA     PA    VA      PA     PA    VA      PA     PA

 ------    --     --  ------    --     --  ------    --     --

 E0..FF -> E0  -> E0  E0..FF -> E0         F0..FF -> F0  -> F0

 C0..DF -> C0  -> C0  C0..DF -> C0         E0..EF -> F0  -> F0

 A0..BF -> A0  -> A0  A0..BF -> A0         D8..DF -> 00  -> 00

 80..9F -> 80  -> 80  80..9F -> 80         D0..D7 -> 00  -> 00

 60..7F -> 60  -> 60  60..7F -> 60

 40..5F -> 40         40..5F -> pc  -> pc  40..5F -> pc

 20..3F -> 20  -> 20  20..3F -> 20

 00..1F -> 00  -> 00  00..1F -> 00



The default location of IO peripherals is above 0xf0000000. This may change

        =====  =====  =====  =====          =====  =====

   VA      PA     PA     PA     PA     VA      PA     PA

 ------    --     --     --     --   ------    --     --

 E0..FF -> E0  -> E0  -> E0          F0..FF -> F0  -> F0

 C0..DF -> C0  -> C0  -> C0          E0..EF -> F0  -> F0

 A0..BF -> A0  -> A0  -> A0          D8..DF -> 00  -> 00

 80..9F -> 80  -> 80  -> 80          D0..D7 -> 00  -> 00

 60..7F -> 60  -> 60  -> 60

 40..5F -> 40         -> pc  -> pc   40..5F -> pc

 20..3F -> 20  -> 20  -> 20

 00..1F -> 00  -> 00  -> 00



The default location of IO peripherals is above 0xf0000000. This may be changed

using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, §6.5

for details on the syntax and semantic of simple-bus nodes. The following

limitations apply:
@@ -62,3 +57,127 @@ limitations apply: 


6. The IO area covers the entire 256MB segment of parent-bus-address; the

   "ranges" triplet length field is ignored





MMUv3 address space layouts.

============================



Default MMUv2-compatible layout.



                      Symbol                   VADDR       Size

+------------------+

| Userspace        |                           0x00000000  TASK_SIZE

+------------------+                           0x40000000

+------------------+

| Page table       |                           0x80000000

+------------------+                           0x80400000

+------------------+

| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

|                  |                                       (4MB * DCACHE_N_COLORS)

+------------------+

| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *

|                  |                                       NR_CPUS *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

+------------------+  FIXADDR_TOP              0xbffff000

+------------------+

| VMALLOC area     |  VMALLOC_START            0xc0000000  128MB - 64KB

+------------------+  VMALLOC_END

| Cache aliasing   |  TLBTEMP_BASE_1           0xc7ff0000  DCACHE_WAY_SIZE

| remap area 1     |

+------------------+

| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE

| remap area 2     |

+------------------+

+------------------+

| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xd0000000  128MB

+------------------+

| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xd8000000  128MB

+------------------+

| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB

+------------------+

| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB

+------------------+





256MB cached + 256MB uncached layout.



                      Symbol                   VADDR       Size

+------------------+

| Userspace        |                           0x00000000  TASK_SIZE

+------------------+                           0x40000000

+------------------+

| Page table       |                           0x80000000

+------------------+                           0x80400000

+------------------+

| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

|                  |                                       (4MB * DCACHE_N_COLORS)

+------------------+

| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *

|                  |                                       NR_CPUS *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

+------------------+  FIXADDR_TOP              0x9ffff000

+------------------+

| VMALLOC area     |  VMALLOC_START            0xa0000000  128MB - 64KB

+------------------+  VMALLOC_END

| Cache aliasing   |  TLBTEMP_BASE_1           0xa7ff0000  DCACHE_WAY_SIZE

| remap area 1     |

+------------------+

| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE

| remap area 2     |

+------------------+

+------------------+

| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xb0000000  256MB

+------------------+

| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  256MB

+------------------+

+------------------+

| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB

+------------------+

| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB

+------------------+





512MB cached + 512MB uncached layout.



                      Symbol                   VADDR       Size

+------------------+

| Userspace        |                           0x00000000  TASK_SIZE

+------------------+                           0x40000000

+------------------+

| Page table       |                           0x80000000

+------------------+                           0x80400000

+------------------+

| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

|                  |                                       (4MB * DCACHE_N_COLORS)

+------------------+

| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *

|                  |                                       NR_CPUS *

|                  |                                       DCACHE_N_COLORS *

|                  |                                       PAGE_SIZE

+------------------+  FIXADDR_TOP              0x8ffff000

+------------------+

| VMALLOC area     |  VMALLOC_START            0x90000000  128MB - 64KB

+------------------+  VMALLOC_END

| Cache aliasing   |  TLBTEMP_BASE_1           0x97ff0000  DCACHE_WAY_SIZE

| remap area 1     |

+------------------+

| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE

| remap area 2     |

+------------------+

+------------------+

| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xa0000000  512MB

+------------------+

| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  512MB

+------------------+

| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB

+------------------+

| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB

+------------------+

arch/xtensa/Kconfig

+78 −17
Original line number Diff line number Diff line
@@ -13,16 +13,19 @@ config XTENSA 
	select GENERIC_IRQ_SHOW

	select GENERIC_PCI_IOMAP

	select GENERIC_SCHED_CLOCK

	select HAVE_DEBUG_KMEMLEAK

	select HAVE_DMA_API_DEBUG

	select HAVE_EXIT_THREAD

	select HAVE_FUNCTION_TRACER

	select HAVE_FUTEX_CMPXCHG if !MMU

	select HAVE_HW_BREAKPOINT if PERF_EVENTS

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_MEMBLOCK

	select HAVE_OPROFILE

	select HAVE_PERF_EVENTS

	select IRQ_DOMAIN

	select MODULES_USE_ELF_RELA

	select NO_BOOTMEM

	select PERF_USE_VMALLOC

	select VIRT_TO_BUS

	help
@@ -209,7 +212,8 @@ config HOTPLUG_CPU 


config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

	bool "Initialize Xtensa MMU inside the Linux kernel code"

	default y

	depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B

	default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM

	help

	  Earlier version initialized the MMU in the exception vector

	  before jumping to _startup in head.S and had an advantage that
@@ -236,6 +240,71 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 


	  If in doubt, say Y.



config KSEG_PADDR

	hex "Physical address of the KSEG mapping"

	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU

	default 0x00000000

	help

	  This is the physical address where KSEG is mapped. Please refer to

	  the chosen KSEG layout help for the required address alignment.

	  Unpacked kernel image (including vectors) must be located completely

	  within KSEG.

	  Physical memory below this address is not available to linux.



	  If unsure, leave the default value here.



config KERNEL_LOAD_ADDRESS

	hex "Kernel load address"

	default 0x60003000 if !MMU

	default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

	default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

	help

	  This is the address where the kernel is loaded.

	  It is virtual address for MMUv2 configurations and physical address

	  for all other configurations.



	  If unsure, leave the default value here.



config VECTORS_OFFSET

	hex "Kernel vectors offset"

	default 0x00003000

	help

	  This is the offset of the kernel image from the relocatable vectors

	  base.



	  If unsure, leave the default value here.



choice

	prompt "KSEG layout"

	depends on MMU

	default XTENSA_KSEG_MMU_V2



config XTENSA_KSEG_MMU_V2

	bool "MMUv2: 128MB cached + 128MB uncached"

	help

	  MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting

	  at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000

	  without cache.

	  KSEG_PADDR must be aligned to 128MB.



config XTENSA_KSEG_256M

	bool "256MB cached + 256MB uncached"

	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

	help

	  TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000

	  with cache and to 0xc0000000 without cache.

	  KSEG_PADDR must be aligned to 256MB.



config XTENSA_KSEG_512M

	bool "512MB cached + 512MB uncached"

	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

	help

	  TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000

	  with cache and to 0xc0000000 without cache.

	  KSEG_PADDR must be aligned to 256MB.



endchoice



config HIGHMEM

	bool "High Memory Support"

	depends on MMU
@@ -331,7 +400,7 @@ config XTENSA_PLATFORM_XT2000 
config XTENSA_PLATFORM_XTFPGA

	bool "XTFPGA"

	select ETHOC if ETHERNET

	select PLATFORM_WANT_DEFAULT_MEM

	select PLATFORM_WANT_DEFAULT_MEM if !MMU

	select SERIAL_CONSOLE

	select XTENSA_CALIBRATE_CCOUNT

	help
@@ -369,6 +438,7 @@ config USE_OF 
	bool "Flattened Device Tree support"

	select OF

	select OF_EARLY_FLATTREE

	select OF_RESERVED_MEM

	help

	  Include support for flattened device tree machine descriptions.
@@ -439,16 +509,9 @@ config DEFAULT_MEM_START 
	default 0x00000000 if MMU

	default 0x60000000 if !MMU

	help

	  This is a fallback start address of the default memory area, it is

	  used when no physical memory size is passed through DTB or through

	  boot parameter from bootloader.



	  In noMMU configuration the following parameters are derived from it:

	  - kernel load address;

	  - kernel entry point address;

	  - relocatable vectors base address;

	  - uBoot load address;

	  - TASK_SIZE.

	  This is the base address of the default memory area.

	  Default memory area has platform-specific meaning, it may be used

	  for e.g. early cache initialization.



	  If unsure, leave the default value here.
@@ -457,11 +520,9 @@ config DEFAULT_MEM_SIZE 
	depends on PLATFORM_WANT_DEFAULT_MEM

	default 0x04000000

	help

	  This is a fallback size of the default memory area, it is used when

	  no physical memory size is passed through DTB or through boot

	  parameter from bootloader.



	  It's also used for TASK_SIZE calculation in noMMU configuration.

	  This is the size of the default memory area.

	  Default memory area has platform-specific meaning, it may be used

	  for e.g. early cache initialization.



	  If unsure, leave the default value here.

arch/xtensa/boot/boot-elf/boot.lds.S

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ SECTIONS 
		*(.ResetVector.text)

	}



	.image KERNELOFFSET: AT (LOAD_MEMORY_ADDRESS)

	.image KERNELOFFSET: AT (CONFIG_KERNEL_LOAD_ADDRESS)

	{

		_image_start = .;

		*(image)

arch/xtensa/boot/boot-elf/bootstrap.S

+6 −1
Original line number Diff line number Diff line
@@ -35,7 +35,12 @@ _ResetVector: 


	.align 4

RomInitAddr:

	.word	LOAD_MEMORY_ADDRESS

#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \

	XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY

	.word	CONFIG_KERNEL_LOAD_ADDRESS

#else

	.word	KERNELOFFSET

#endif

RomBootParam:

	.word _bootparam

_bootparam:

arch/xtensa/boot/boot-uboot/Makefile

+1 −9
Original line number Diff line number Diff line
@@ -4,15 +4,7 @@ 
# for more details.

#



ifdef CONFIG_MMU

ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX

UIMAGE_LOADADDR = 0x00003000

else

UIMAGE_LOADADDR = 0xd0003000

endif

else

UIMAGE_LOADADDR = $(shell printf "0x%x" $$(( ${CONFIG_DEFAULT_MEM_START} + 0x3000 )) )

endif

UIMAGE_LOADADDR = $(CONFIG_KERNEL_LOAD_ADDRESS)

UIMAGE_COMPRESSION = gzip



$(obj)/../uImage: vmlinux.bin.gz FORCE

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