net: dsa: mv88e6xxx: Preserve priority when setting CPU port. (d8dc2c96) · Commits · 戴 / test

The 6390 family uses an extended register to set the port connected to the CPU. The lower 5 bits indicate the port, the upper three bits are the priority of the frames as they pass through the switch, what egress queue they should use, etc. Since frames being set to the CPU are typically management frames, BPDU, IGMP, ARP, etc set the priority to 7, the reset default, and the highest. Fixes: ("net: dsa: mv88e6xxx: Monitor and Management tables") Signed-off-by:

Andrew Lunn <andrew@lunn.ch> Tested-by:

Chris Healy <cphealy@gmail.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/dsa/mv88e6xxx/global1.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -360,6 +360,11 @@ int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
		{
		u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;

		/* Use the default high priority for management frames sent to
		* the CPU.
		*/
		port \|= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;

		return mv88e6390_g1_monitor_write(chip, ptr, port);
		}

drivers/net/dsa/mv88e6xxx/global1.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -211,6 +211,7 @@
		#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
		#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
		#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
		#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0
		#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff

		/* Offset 0x1C: Global Control 2 */

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