Commit d8c22b32 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'tags/meson-clk-5.1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull Amlogic clk driver updates from Neil Armstrong:
 - add 32k clock generation for AXG
 - add support for the Mali GPU clocks for Meson8
 - claim input clocks through DT for AXG and GXBB
 - rework drivers dependencies among meson clock drivers
 - add G12A EE clock controller driver

* tag 'tags/meson-clk-5.1' of https://github.com/BayLibre/clk-meson:
  clk: meson: factorise meson64 peripheral clock controller drivers
  clk: meson: g12a: add peripheral clock controller
  dt-bindings: clk: meson: add g12a periph clock controller bindings
  clk: meson: pll: update driver for the g12a
  clk: meson: rework and clean drivers dependencies
  clk: meson: axg-audio does not require syscon
  clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
  clk: export some clk_hw function symbols for module drivers
  clk: meson: ao-clkc: claim clock controller input clocks from DT
  clk: meson: axg: claim clock controller input clock from DT
  clk: meson: gxbb: claim clock controller input clock from DT
  clk: meson: meson8b: add the GPU clock tree
  clk: meson: meson8b: use a separate clock table for Meson8
  clk: meson: axg-ao: add 32k generation subtree
  clk: meson: gxbb-ao: replace cec-32k with the dual divider
  clk: meson: add dual divider clock driver
  clk: meson: clean-up clock registration
  dt-bindings: clk: meson: add ao slow clock path ids
parents bfeffd15 6682bd4d
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+1 −0
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@@ -9,6 +9,7 @@ Required Properties:
		"amlogic,gxbb-clkc" for GXBB SoC,
		"amlogic,gxl-clkc" for GXL and GXM SoC,
		"amlogic,axg-clkc" for AXG SoC.
		"amlogic,g12a-clkc" for G12A SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
  * "xtal": the platform xtal
+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ obj-$(CONFIG_ARCH_K3) += keystone/
obj-$(CONFIG_ARCH_KEYSTONE)		+= keystone/
obj-$(CONFIG_MACH_LOONGSON32)		+= loongson1/
obj-y					+= mediatek/
obj-$(CONFIG_COMMON_CLK_AMLOGIC)	+= meson/
obj-$(CONFIG_ARCH_MESON)		+= meson/
obj-$(CONFIG_MACH_PIC32)		+= microchip/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP)			+= mmp/
+3 −0
Original line number Diff line number Diff line
@@ -394,16 +394,19 @@ bool clk_hw_is_prepared(const struct clk_hw *hw)
{
	return clk_core_is_prepared(hw->core);
}
EXPORT_SYMBOL_GPL(clk_hw_is_prepared);

bool clk_hw_rate_is_protected(const struct clk_hw *hw)
{
	return clk_core_rate_is_protected(hw->core);
}
EXPORT_SYMBOL_GPL(clk_hw_rate_is_protected);

bool clk_hw_is_enabled(const struct clk_hw *hw)
{
	return clk_core_is_enabled(hw->core);
}
EXPORT_SYMBOL_GPL(clk_hw_is_enabled);

bool __clk_is_enabled(struct clk *clk)
{
+75 −24
Original line number Diff line number Diff line
config COMMON_CLK_AMLOGIC
	bool
	depends on ARCH_MESON || COMPILE_TEST
	select COMMON_CLK_REGMAP_MESON
config COMMON_CLK_MESON_INPUT
	tristate

config COMMON_CLK_AMLOGIC_AUDIO
	bool
	depends on ARCH_MESON || COMPILE_TEST
	select COMMON_CLK_AMLOGIC
config COMMON_CLK_MESON_REGMAP
	tristate
	select REGMAP

config COMMON_CLK_MESON_AO
	bool
	depends on OF
	depends on ARCH_MESON || COMPILE_TEST
	select COMMON_CLK_REGMAP_MESON
config COMMON_CLK_MESON_DUALDIV
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_MPLL
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_PHASE
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_PLL
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_SCLK_DIV
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_VID_PLL_DIV
	tristate
	select COMMON_CLK_MESON_REGMAP

config COMMON_CLK_MESON_AO_CLKC
	tristate
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_INPUT
	select RESET_CONTROLLER

config COMMON_CLK_REGMAP_MESON
	bool
	select REGMAP
config COMMON_CLK_MESON_EE_CLKC
	tristate
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_INPUT

config COMMON_CLK_MESON8B
	bool
	select COMMON_CLK_AMLOGIC
	depends on ARCH_MESON
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_MPLL
	select COMMON_CLK_MESON_PLL
	select MFD_SYSCON
	select RESET_CONTROLLER
	help
	  Support for the clock controller on AmLogic S802 (Meson8),
@@ -30,8 +55,14 @@ config COMMON_CLK_MESON8B

config COMMON_CLK_GXBB
	bool
	select COMMON_CLK_AMLOGIC
	select COMMON_CLK_MESON_AO
	depends on ARCH_MESON
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_DUALDIV
	select COMMON_CLK_MESON_VID_PLL_DIV
	select COMMON_CLK_MESON_MPLL
	select COMMON_CLK_MESON_PLL
	select COMMON_CLK_MESON_AO_CLKC
	select COMMON_CLK_MESON_EE_CLKC
	select MFD_SYSCON
	help
	  Support for the clock controller on AmLogic S905 devices, aka gxbb.
@@ -39,8 +70,13 @@ config COMMON_CLK_GXBB

config COMMON_CLK_AXG
	bool
	select COMMON_CLK_AMLOGIC
	select COMMON_CLK_MESON_AO
	depends on ARCH_MESON
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_DUALDIV
	select COMMON_CLK_MESON_MPLL
	select COMMON_CLK_MESON_PLL
	select COMMON_CLK_MESON_AO_CLKC
	select COMMON_CLK_MESON_EE_CLKC
	select MFD_SYSCON
	help
	  Support for the clock controller on AmLogic A113D devices, aka axg.
@@ -48,9 +84,24 @@ config COMMON_CLK_AXG

config COMMON_CLK_AXG_AUDIO
	tristate "Meson AXG Audio Clock Controller Driver"
	depends on COMMON_CLK_AXG
	select COMMON_CLK_AMLOGIC_AUDIO
	select MFD_SYSCON
	depends on ARCH_MESON
	select COMMON_CLK_MESON_INPUT
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_PHASE
	select COMMON_CLK_MESON_SCLK_DIV
	select REGMAP_MMIO
	help
	  Support for the audio clock controller on AmLogic A113D devices,
	  aka axg, Say Y if you want audio subsystem to work.

config COMMON_CLK_G12A
	bool
	depends on ARCH_MESON
	select COMMON_CLK_MESON_REGMAP
	select COMMON_CLK_MESON_MPLL
	select COMMON_CLK_MESON_PLL
	select COMMON_CLK_MESON_EE_CLKC
	select MFD_SYSCON
	help
	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
	  devices, aka g12a. Say Y if you want peripherals to work.
+18 −11
Original line number Diff line number Diff line
#
# Makefile for Meson specific clk
#
# Amlogic clock drivers

obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o
obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o

# Amlogic Clock controllers

obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o
obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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