Commit d8897975 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge remote-tracking branch 'arm64/for-next/fixes' into for-next/core 

* arm64/for-next/fixes: (26 commits)
  arm64: mte: fix prctl(PR_GET_TAGGED_ADDR_CTRL) if TCF0=NONE
  arm64: mte: Fix typo in macro definition
  arm64: entry: fix EL1 debug transitions
  arm64: entry: fix NMI {user, kernel}->kernel transitions
  arm64: entry: fix non-NMI kernel<->kernel transitions
  arm64: ptrace: prepare for EL1 irq/rcu tracking
  arm64: entry: fix non-NMI user<->kernel transitions
  arm64: entry: move el1 irq/nmi logic to C
  arm64: entry: prepare ret_to_user for function call
  arm64: entry: move enter_from_user_mode to entry-common.c
  arm64: entry: mark entry code as noinstr
  arm64: mark idle code as noinstr
  arm64: syscall: exit userspace before unmasking exceptions
  arm64: pgtable: Ensure dirty bit is preserved across pte_wrprotect()
  arm64: pgtable: Fix pte_accessible()
  ACPI/IORT: Fix doc warnings in iort.c
  arm64/fpsimd: add <asm/insn.h> to <asm/kprobes.h> to fix fpsimd build
  arm64: cpu_errata: Apply Erratum 845719 to KRYO2XX Silver
  arm64: proton-pack: Add KRYO2XX silver CPUs to spectre-v2 safe-list
  arm64: kpti: Add KRYO2XX gold/silver CPU cores to kpti safelist
  ...

# Conflicts:
#	arch/arm64/include/asm/exception.h
#	arch/arm64/kernel/sdei.c
parents d45056ad 929c1f33

arch/arm64/include/asm/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 
/*

 * CPU feature detected at boot time based on feature of one or more CPUs.

 * All possible conflicts for a late CPU are ignored.

 * NOTE: this means that a late CPU with the feature will *not* cause the

 * capability to be advertised by cpus_have_*cap()!

 */

#define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE		\

	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -86,6 +86,8 @@ 
#define QCOM_CPU_PART_FALKOR_V1		0x800

#define QCOM_CPU_PART_FALKOR		0xC00

#define QCOM_CPU_PART_KRYO		0x200

#define QCOM_CPU_PART_KRYO_2XX_GOLD	0x800

#define QCOM_CPU_PART_KRYO_2XX_SILVER	0x801

#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803

#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804

#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805
@@ -116,6 +118,8 @@ 
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)

#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)

#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)

#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)

#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)

#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)

arch/arm64/include/asm/daifflags.h

+3 −0
Original line number Diff line number Diff line
@@ -128,6 +128,9 @@ static inline void local_daif_inherit(struct pt_regs *regs) 
{

	unsigned long flags = regs->pstate & DAIF_MASK;



	if (interrupts_enabled(regs))

		trace_hardirqs_on();



	/*

	 * We can't use local_daif_restore(regs->pstate) here as

	 * system_has_prio_mask_debugging() won't restore the I bit if it can

arch/arm64/include/asm/exception.h

+5 −0
Original line number Diff line number Diff line
@@ -31,7 +31,12 @@ static inline u32 disr_to_esr(u64 disr) 
	return esr;

}



asmlinkage void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs);

asmlinkage void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs);

asmlinkage void enter_from_user_mode(void);

asmlinkage void exit_to_user_mode(void);

void arm64_enter_nmi(struct pt_regs *regs);

void arm64_exit_nmi(struct pt_regs *regs);

void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs);

void do_undefinstr(struct pt_regs *regs);

void do_bti(struct pt_regs *regs);

arch/arm64/include/asm/pgtable.h

+18 −16
Original line number Diff line number Diff line
@@ -115,8 +115,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 
#define pte_valid(pte)		(!!(pte_val(pte) & PTE_VALID))

#define pte_valid_not_user(pte) \

	((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)

#define pte_valid_young(pte) \

	((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))

#define pte_valid_user(pte) \

	((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
@@ -124,9 +122,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 
 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending

 * so that we don't erroneously return false for pages that have been

 * remapped as PROT_NONE but are yet to be flushed from the TLB.

 * Note that we can't make any assumptions based on the state of the access

 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the

 * TLB.

 */

#define pte_accessible(mm, pte)	\

	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))

	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))



/*

 * p??_access_permitted() is true for valid user mappings (subject to the
@@ -164,13 +165,6 @@ static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 
	return pmd;

}



static inline pte_t pte_wrprotect(pte_t pte)

{

	pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));

	pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));

	return pte;

}



static inline pte_t pte_mkwrite(pte_t pte)

{

	pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
@@ -196,6 +190,20 @@ static inline pte_t pte_mkdirty(pte_t pte) 
	return pte;

}



static inline pte_t pte_wrprotect(pte_t pte)

{

	/*

	 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY

	 * clear), set the PTE_DIRTY bit.

	 */

	if (pte_hw_dirty(pte))

		pte = pte_mkdirty(pte);



	pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));

	pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));

	return pte;

}



static inline pte_t pte_mkold(pte_t pte)

{

	return clear_pte_bit(pte, __pgprot(PTE_AF));
@@ -846,12 +854,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres 
	pte = READ_ONCE(*ptep);

	do {

		old_pte = pte;

		/*

		 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY

		 * clear), set the PTE_DIRTY bit.

		 */

		if (pte_hw_dirty(pte))

			pte = pte_mkdirty(pte);

		pte = pte_wrprotect(pte);

		pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),

					       pte_val(old_pte), pte_val(pte));

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