clk: imx6: initialize GPU clocks (d8846023) · Commits · 戴 / test

Initialize the GPU clock muxes to sane inputs. Until now they have not been changed from their default values, which means that both GPU3D shader and GPU2D core were fed by clock inputs whose rates exceed the maximium allowed frequency of the cores by as much as 200MHz. This fixes a severe GPU stability issue on i.MX6DL. Cc: stable@vger.kernel.org Signed-off-by:

Lucas Stach <l.stach@pengutronix.de> Acked-by:

Shawn Guo <shawnguo@kernel.org> Signed-off-by:

Stephen Boyd <sboyd@codeaurora.org>

drivers/clk/imx/clk-imx6q.c

+18 −0

Original line number	Diff line number	Diff line
		@@ -633,6 +633,24 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
		if (IS_ENABLED(CONFIG_PCI_IMX6))
		clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);

		/*
		* Initialize the GPU clock muxes, so that the maximum specified clock
		* rates for the respective SoC are not exceeded.
		*/
		if (clk_on_imx6dl()) {
		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
		clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
		clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
		clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
		} else if (clk_on_imx6q()) {
		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
		clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
		clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL],
		clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
		clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
		clk[IMX6QDL_CLK_PLL3_USB_OTG]);
		}

		imx_register_uart_clocks(uart_clks);
		}
		CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);

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