Commit d80b34c9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "Here is a handful of minor arm64 fixes discovered and fixed over the
  Christmas break.  The main part is adding some missing #includes that
  we seem to be getting transitively but have started causing problems
  in -next.

   - Fix early mapping fixmap corruption by EFI runtime services
   - Fix __NR_compat_syscalls off-by-one
   - Add missing sanity checks for some 32-bit registers
   - Add some missing #includes which we get transitively
   - Remove unused prepare_to_copy() macro"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/efi: add missing call to early_ioremap_reset()
  arm64: fix missing asm/io.h include in kernel/smp_spin_table.c
  arm64: fix missing asm/alternative.h include in kernel/module.c
  arm64: fix missing linux/bug.h include in asm/arch_timer.h
  arm64: fix missing asm/pgtable-hwdef.h include in asm/processor.h
  arm64: sanity checks: add missing AArch32 registers
  arm64: Remove unused prepare_to_copy()
  arm64: Correct __NR_compat_syscalls for bpf
parents aa929135 0e63ea48

arch/arm64/include/asm/arch_timer.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


#include <asm/barrier.h>



#include <linux/bug.h>

#include <linux/init.h>

#include <linux/types.h>

arch/arm64/include/asm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;



	u32		reg_id_dfr0;

	u32		reg_id_isar0;

	u32		reg_id_isar1;

	u32		reg_id_isar2;
@@ -51,6 +52,10 @@ struct cpuinfo_arm64 { 
	u32		reg_id_mmfr3;

	u32		reg_id_pfr0;

	u32		reg_id_pfr1;



	u32		reg_mvfr0;

	u32		reg_mvfr1;

	u32		reg_mvfr2;

};



DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);

arch/arm64/include/asm/processor.h

+1 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 


#include <asm/fpsimd.h>

#include <asm/hw_breakpoint.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>

#include <asm/types.h>
@@ -123,9 +124,6 @@ struct task_struct; 
/* Free all resources held by a thread. */

extern void release_thread(struct task_struct *);



/* Prepare to copy thread state - unlazy all lazy status */

#define prepare_to_copy(tsk)	do { } while (0)



unsigned long get_wchan(struct task_struct *p);



#define cpu_relax()			barrier()

arch/arm64/include/asm/unistd.h

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
#define __ARM_NR_compat_cacheflush	(__ARM_NR_COMPAT_BASE+2)

#define __ARM_NR_compat_set_tls		(__ARM_NR_COMPAT_BASE+5)



#define __NR_compat_syscalls		386

#define __NR_compat_syscalls		387

#endif



#define __ARCH_WANT_SYS_CLONE

arch/arm64/kernel/cpuinfo.c

+10 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur) 
	 * If we have AArch32, we care about 32-bit features for compat. These

	 * registers should be RES0 otherwise.

	 */

	diff |= CHECK(id_dfr0, boot, cur, cpu);

	diff |= CHECK(id_isar0, boot, cur, cpu);

	diff |= CHECK(id_isar1, boot, cur, cpu);

	diff |= CHECK(id_isar2, boot, cur, cpu);
@@ -165,6 +166,10 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur) 
	diff |= CHECK(id_pfr0, boot, cur, cpu);

	diff |= CHECK(id_pfr1, boot, cur, cpu);



	diff |= CHECK(mvfr0, boot, cur, cpu);

	diff |= CHECK(mvfr1, boot, cur, cpu);

	diff |= CHECK(mvfr2, boot, cur, cpu);



	/*

	 * Mismatched CPU features are a recipe for disaster. Don't even

	 * pretend to support them.
@@ -189,6 +194,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);



	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);

	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);

	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);

	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
@@ -202,6 +208,10 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);

	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);



	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);

	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);

	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);



	cpuinfo_detect_icache_policy(info);



	check_local_cpu_errata();

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