Commit d7fb5b18 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/64: optimise LOAD_REG_IMMEDIATE_SYM() 



Optimise LOAD_REG_IMMEDIATE_SYM() using a temporary register to
parallelise operations.

It reduces the path from 5 to 3 instructions.

Suggested-by: default avatarSegher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/bad41ed02531bb0382420cbab50a0d7153b71767.1566311636.git.christophe.leroy@c-s.fr
parent ba18025f

arch/powerpc/include/asm/ppc_asm.h

+6 −6
Original line number Diff line number Diff line
@@ -347,12 +347,12 @@ n: 


#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr



#define LOAD_REG_IMMEDIATE_SYM(reg,expr)	\

	lis     reg,(expr)@highest;		\

	ori     reg,reg,(expr)@higher;	\

	rldicr  reg,reg,32,31;		\

	oris    reg,reg,(expr)@__AS_ATHIGH;	\

	ori     reg,reg,(expr)@l;

#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr)	\

	lis	tmp, (expr)@highest;		\

	lis	reg, (expr)@__AS_ATHIGH;	\

	ori	tmp, tmp, (expr)@higher;	\

	ori	reg, reg, (expr)@l;		\

	rldimi	reg, tmp, 32, 0



#define LOAD_REG_ADDR(reg,name)			\

	ld	reg,name@got(r2)

arch/powerpc/kernel/exceptions-64e.S

+13 −9
Original line number Diff line number Diff line
@@ -750,12 +750,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 
	ld	r15,PACATOC(r13)

	ld	r14,interrupt_base_book3e@got(r15)

	ld	r15,__end_interrupts@got(r15)

#else

	LOAD_REG_IMMEDIATE_SYM(r14,interrupt_base_book3e)

	LOAD_REG_IMMEDIATE_SYM(r15,__end_interrupts)

#endif

	cmpld	cr0,r10,r14

	cmpld	cr1,r10,r15

#else

	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)

	cmpld	cr0, r10, r14

	LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)

	cmpld	cr1, r10, r14

#endif

	blt+	cr0,1f

	bge+	cr1,1f
@@ -820,12 +822,14 @@ kernel_dbg_exc: 
	ld	r15,PACATOC(r13)

	ld	r14,interrupt_base_book3e@got(r15)

	ld	r15,__end_interrupts@got(r15)

#else

	LOAD_REG_IMMEDIATE_SYM(r14,interrupt_base_book3e)

	LOAD_REG_IMMEDIATE_SYM(r15,__end_interrupts)

#endif

	cmpld	cr0,r10,r14

	cmpld	cr1,r10,r15

#else

	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)

	cmpld	cr0, r10, r14

	LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)

	cmpld	cr1, r10, r14

#endif

	blt+	cr0,1f

	bge+	cr1,1f
@@ -1449,7 +1453,7 @@ a2_tlbinit_code_start: 
a2_tlbinit_after_linear_map:



	/* Now we branch the new virtual address mapped by this entry */

	LOAD_REG_IMMEDIATE_SYM(r3,1f)

	LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)

	mtctr	r3

	bctr

arch/powerpc/kernel/head_64.S

+1 −1
Original line number Diff line number Diff line
@@ -635,7 +635,7 @@ __after_prom_start: 
	sub	r5,r5,r11

#else

	/* just copy interrupts */

	LOAD_REG_IMMEDIATE_SYM(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))

	LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))

#endif

	b	5f

3:

CRA Git | Maintained and supported by SUSTech CRA and CCSE