drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround (d7f52e29) · Commits · 戴 / test

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+39 −1

Original line number	Diff line number	Diff line
		@@ -2693,6 +2693,44 @@ static int sienna_cichlid_gpo_control(struct smu_context *smu,

		return ret;
		}

		static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
		{
		uint32_t smu_version;
		int ret = 0;

		ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
		if (ret)
		return ret;

		/*
		* Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
		* onwards PMFWs.
		*/
		if (smu_version < 0x003A2D00)
		return 0;

		return smu_cmn_send_smc_msg_with_param(smu,
		SMU_MSG_Enable2ndUSB20Port,
		smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
		1 : 0,
		NULL);
		}

		static int sienna_cichlid_system_features_control(struct smu_context *smu,
		bool en)
		{
		int ret = 0;

		if (en) {
		ret = sienna_cichlid_notify_2nd_usb20_port(smu);
		if (ret)
		return ret;
		}

		return smu_v11_0_system_features_control(smu, en);
		}

		static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
		.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
		.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
		@@ -2733,7 +2771,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
		.set_driver_table_location = smu_v11_0_set_driver_table_location,
		.set_tool_table_location = smu_v11_0_set_tool_table_location,
		.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
		.system_features_control = smu_v11_0_system_features_control,
		.system_features_control = sienna_cichlid_system_features_control,
		.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
		.send_smc_msg = smu_cmn_send_smc_msg,
		.init_display_count = NULL,

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