ARC: [plat-axs103] refactor the quad core DT quirk code (d7de73b5) · Commits · 戴 / test

arch/arc/plat-axs10x/axs10x.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -317,19 +317,21 @@ static void __init axs103_early_init(void)
		* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
		* of fudging the freq in DT
		*/
		#define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000

		unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
		if (num_cores > 2) {
		u32 freq = 50, orig;
		u32 freq;
		int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
		const struct fdt_property *prop;

		prop = fdt_get_property(initial_boot_params, off,
		"assigned-clock-rates", NULL);
		orig = be32_to_cpu((u32)(prop->data)) / 1000000;
		freq = be32_to_cpu((u32 )(prop->data));

		/* Patching .dtb in-place with new core clock value */
		if (freq != orig ) {
		freq = cpu_to_be32(freq * 1000000);
		if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
		freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
		fdt_setprop_inplace(initial_boot_params, off,
		"assigned-clock-rates", &freq, sizeof(freq));
		}