Commit d7ca2d19 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2020-01-14' of https://gitlab.freedesktop.org/drm/msm into drm-next 



+ sc7180 display + DSI support
+ a618 (sc7180) support
+ more UBWC (bandwidth compression) support
+ various cleanups to handle devices that use vs don't
  use zap fw, etc
+ usual random cleanups and fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGvv03ifuP0tp7-dmqZtr1iS=s8Vc=az8BNGtEoSMD-dkw@mail.gmail.com
parents 3d474313 5f9935f5

Documentation/devicetree/bindings/display/msm/dpu.txt

+2 −2
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC. 


MDSS:

Required properties:

- compatible: "qcom,sdm845-mdss"

- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"

- reg: physical base address and length of contoller's registers.

- reg-names: register region names. The following region is required:

  * "mdss"
@@ -41,7 +41,7 @@ Optional properties: 


MDP:

Required properties:

- compatible: "qcom,sdm845-dpu"

- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"

- reg: physical base address and length of controller's registers.

- reg-names : register region names. The following region is required:

  * "mdp"

Documentation/devicetree/bindings/display/msm/gpu.txt

+8 −1
Original line number Diff line number Diff line
@@ -23,13 +23,18 @@ Required properties: 
- iommus: optional phandle to an adreno iommu instance

- operating-points-v2: optional phandle to the OPP operating points

- interconnects: optional phandle to an interconnect provider.  See

  ../interconnect/interconnect.txt for details.

  ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms

  will have two paths; all others will have one path.

- interconnect-names: The names of the interconnect paths that correspond to the

  interconnects property. Values must be gfx-mem and ocmem.

- qcom,gmu: For GMU attached devices a phandle to the GMU device that will

  control the power for the GPU. Applicable targets:

    - qcom,adreno-630.2

- zap-shader: For a5xx and a6xx devices this node contains a memory-region that

  points to reserved memory to store the zap shader that can be used to help

  bring the GPU out of secure mode.

- firmware-name: optional property of the 'zap-shader' node, listing the

  relative path of the device specific zap firmware.



Example 3xx/4xx/a5xx:
@@ -76,11 +81,13 @@ Example a6xx (with GMU): 
		operating-points-v2 = <&gpu_opp_table>;



		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;

		interconnect-names = "gfx-mem";



		qcom,gmu = <&gmu>;



		zap-shader {

			memory-region = <&zap_shader_region>;

			firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"

		};

	};

};

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+8 −0
Original line number Diff line number Diff line
@@ -506,6 +506,14 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
		goto fail;

	}



	/*

	 * Set the ICC path to maximum speed for now by multiplying the fastest

	 * frequency by the bus width (8). We'll want to scale this later on to

	 * improve battery life.

	 */

	icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);



	return gpu;



fail:

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+8 −0
Original line number Diff line number Diff line
@@ -591,6 +591,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
		goto fail;

	}



	/*

	 * Set the ICC path to maximum speed for now by multiplying the fastest

	 * frequency by the bus width (8). We'll want to scale this later on to

	 * improve battery life.

	 */

	icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);



	return gpu;



fail:

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+9 −2
Original line number Diff line number Diff line
@@ -753,11 +753,18 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
		gpu->funcs->flush(gpu, gpu->rb[0]);

		if (!a5xx_idle(gpu, gpu->rb[0]))

			return -EINVAL;

	} else {

		/* Print a warning so if we die, we know why */

	} else if (ret == -ENODEV) {

		/*

		 * This device does not use zap shader (but print a warning

		 * just in case someone got their dt wrong.. hopefully they

		 * have a debug UART to realize the error of their ways...

		 * if you mess this up you are about to crash horribly)

		 */

		dev_warn_once(gpu->dev->dev,

			"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");

		gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);

	} else {

		return ret;

	}



	/* Last step - yield the ringbuffer */

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