Commit d7c96611 authored by Chris Metcalf's avatar Chris Metcalf
Browse files

tile: remove support for TILE64 



This chip is no longer being actively developed for (it was superceded
by the TILEPro64 in 2008), and in any case the existing compiler and
toolchain in the community do not support it.  It's unlikely that the
kernel works with TILE64 at this point as the configuration has not been
tested in years.  The support is also awkward as it requires maintaining
a significant number of ifdefs.  So, just remove it altogether.

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent d6a0aa31

arch/tile/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ config SYSVIPC_COMPAT 
	def_bool y

	depends on COMPAT && SYSVIPC



# We do not currently support disabling HIGHMEM on tile64 and tilepro.

# We do not currently support disabling HIGHMEM on tilepro.

config HIGHMEM

	bool # "Support for more than 512 MB of RAM"

	default !TILEGX

arch/tile/include/asm/atomic_32.h

+0 −17
Original line number Diff line number Diff line
@@ -252,21 +252,6 @@ static inline void atomic64_set(atomic64_t *v, u64 n) 
 * Internal definitions only beyond this point.

 */



#define ATOMIC_LOCKS_FOUND_VIA_TABLE() \

  (!CHIP_HAS_CBOX_HOME_MAP() && defined(CONFIG_SMP))



#if ATOMIC_LOCKS_FOUND_VIA_TABLE()



/* Number of entries in atomic_lock_ptr[]. */

#define ATOMIC_HASH_L1_SHIFT 6

#define ATOMIC_HASH_L1_SIZE (1 << ATOMIC_HASH_L1_SHIFT)



/* Number of locks in each struct pointed to by atomic_lock_ptr[]. */

#define ATOMIC_HASH_L2_SHIFT (CHIP_L2_LOG_LINE_SIZE() - 2)

#define ATOMIC_HASH_L2_SIZE (1 << ATOMIC_HASH_L2_SHIFT)



#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */



/*

 * Number of atomic locks in atomic_locks[]. Must be a power of two.

 * There is no reason for more than PAGE_SIZE / 8 entries, since that
@@ -281,8 +266,6 @@ static inline void atomic64_set(atomic64_t *v, u64 n) 
extern int atomic_locks[];

#endif



#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */



/*

 * All the code that may fault while holding an atomic lock must

 * place the pointer to the lock in ATOMIC_LOCK_REG so the fault code

arch/tile/include/asm/barrier.h

+0 −4
Original line number Diff line number Diff line
@@ -77,7 +77,6 @@ 


#define __sync()	__insn_mf()



#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()

#include <hv/syscall_public.h>

/*

 * Issue an uncacheable load to each memory controller, then
@@ -96,7 +95,6 @@ static inline void __mb_incoherent(void) 
		       "r20", "r21", "r22", "r23", "r24",

		       "r25", "r26", "r27", "r28", "r29");

}

#endif



/* Fence to guarantee visibility of stores to incoherent memory. */

static inline void
@@ -104,7 +102,6 @@ mb_incoherent(void) 
{

	__insn_mf();



#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()

	{

#if CHIP_HAS_TILE_WRITE_PENDING()

		const unsigned long WRITE_TIMEOUT_CYCLES = 400;
@@ -116,7 +113,6 @@ mb_incoherent(void) 
#endif /* CHIP_HAS_TILE_WRITE_PENDING() */

		(void) __mb_incoherent();

	}

#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */

}



#define fast_wmb()	__sync()

arch/tile/include/asm/elf.h

+0 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ typedef unsigned long elf_greg_t; 
#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))

typedef elf_greg_t elf_gregset_t[ELF_NGREG];



#define EM_TILE64  187

#define EM_TILEPRO 188

#define EM_TILEGX  191

arch/tile/include/asm/homecache.h

+1 −2
Original line number Diff line number Diff line
@@ -33,8 +33,7 @@ struct zone; 


/*

 * Is this page immutable (unwritable) and thus able to be cached more

 * widely than would otherwise be possible?  On tile64 this means we

 * mark the PTE to cache locally; on tilepro it means we have "nc" set.

 * widely than would otherwise be possible?  This means we have "nc" set.

 */

#define PAGE_HOME_IMMUTABLE -2

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