Commit d7c2878c authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by Li Yang
Browse files

soc: fsl: qe: remove unused qe_ic_set_* functions 



There are no current callers of these functions, and they use the
ppc-specific virq_to_hw(). So removing them gets us one step closer to
building QE support for ARM.

If the functionality is ever actually needed, the code can be dug out
of git and then adapted to work on all architectures, but for future
reference please note that I believe qe_ic_set_priority is buggy: The
"priority < 4" should be "priority <= 4", and in the else branch 24
should be replaced by 28, at least if I'm reading the data sheet right.

Reviewed-by: default avatarTimur Tabi <timur@kernel.org>
Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent 523eef1d

drivers/soc/fsl/qe/qe_ic.c

+0 −94
Original line number Diff line number Diff line
@@ -445,97 +445,3 @@ static int __init qe_ic_of_init(void) 
	return 0;

}

subsys_initcall(qe_ic_of_init);
 


void qe_ic_set_highest_priority(unsigned int virq, int high)

{

	struct qe_ic *qe_ic = qe_ic_from_irq(virq);

	unsigned int src = virq_to_hw(virq);

	u32 temp = 0;



	temp = qe_ic_read(qe_ic->regs, QEIC_CICR);



	temp &= ~CICR_HP_MASK;

	temp |= src << CICR_HP_SHIFT;



	temp &= ~CICR_HPIT_MASK;

	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;



	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);

}



/* Set Priority level within its group, from 1 to 8 */

int qe_ic_set_priority(unsigned int virq, unsigned int priority)

{

	struct qe_ic *qe_ic = qe_ic_from_irq(virq);

	unsigned int src = virq_to_hw(virq);

	u32 temp;



	if (priority > 8 || priority == 0)

		return -EINVAL;

	if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),

		      "%s: Invalid hw irq number for QEIC\n", __func__))

		return -EINVAL;

	if (qe_ic_info[src].pri_reg == 0)

		return -EINVAL;



	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);



	if (priority < 4) {

		temp &= ~(0x7 << (32 - priority * 3));

		temp |= qe_ic_info[src].pri_code << (32 - priority * 3);

	} else {

		temp &= ~(0x7 << (24 - priority * 3));

		temp |= qe_ic_info[src].pri_code << (24 - priority * 3);

	}



	qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);



	return 0;

}



/* Set a QE priority to use high irq, only priority 1~2 can use high irq */

int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)

{

	struct qe_ic *qe_ic = qe_ic_from_irq(virq);

	unsigned int src = virq_to_hw(virq);

	u32 temp, control_reg = QEIC_CICNR, shift = 0;



	if (priority > 2 || priority == 0)

		return -EINVAL;

	if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),

		      "%s: Invalid hw irq number for QEIC\n", __func__))

		return -EINVAL;



	switch (qe_ic_info[src].pri_reg) {

	case QEIC_CIPZCC:

		shift = CICNR_ZCC1T_SHIFT;

		break;

	case QEIC_CIPWCC:

		shift = CICNR_WCC1T_SHIFT;

		break;

	case QEIC_CIPYCC:

		shift = CICNR_YCC1T_SHIFT;

		break;

	case QEIC_CIPXCC:

		shift = CICNR_XCC1T_SHIFT;

		break;

	case QEIC_CIPRTA:

		shift = CRICR_RTA1T_SHIFT;

		control_reg = QEIC_CRICR;

		break;

	case QEIC_CIPRTB:

		shift = CRICR_RTB1T_SHIFT;

		control_reg = QEIC_CRICR;

		break;

	default:

		return -EINVAL;

	}



	shift += (2 - priority) * 2;

	temp = qe_ic_read(qe_ic->regs, control_reg);

	temp &= ~(SIGNAL_MASK << shift);

	temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;

	qe_ic_write(qe_ic->regs, control_reg, temp);



	return 0;

}

include/soc/fsl/qe/qe_ic.h

+0 −4
Original line number Diff line number Diff line
@@ -63,8 +63,4 @@ static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) 
{ return 0; }

#endif /* CONFIG_QUICC_ENGINE */



void qe_ic_set_highest_priority(unsigned int virq, int high);

int qe_ic_set_priority(unsigned int virq, unsigned int priority);

int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);



#endif /* _ASM_POWERPC_QE_IC_H */

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