Commit d76e9b9f authored Jan 30, 2015 by James Hogan Committed by Ralf Baechle Jan 30, 2015

MIPS: traps: Fix inline asm ctc1 missing .set hardfloat



Commit 842dfc11 ("MIPS: Fix build with binutils 2.24.51+") in v3.18
enabled -msoft-float and sprinkled ".set hardfloat" where necessary to
use FP instructions. However it missed enable_restore_fp_context() which
since v3.17 does a ctc1 with inline assembly, causing the following
assembler errors on Mentor's 2014.05 toolchain:

{standard input}: Assembler messages:
{standard input}:2913: Error: opcode not supported on this processor: mips32r2 (mips32r2) `ctc1 $2,$31'
scripts/Makefile.build:257: recipe for target 'arch/mips/kernel/traps.o' failed

Fix that to use the new write_32bit_cp1_register() macro so that ".set
hardfloat" is automatically added when -msoft-float is in use.

Fixes 842dfc11 ("MIPS: Fix build with binutils 2.24.51+")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.18+, depends on "MIPS: mipsregs.h: Add write_32bit_cp1_register()"
Patchwork: https://patchwork.linux-mips.org/patch/9173/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 5e32033e

arch/mips/kernel/traps.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1231,7 +1231,8 @@ static int enable_restore_fp_context(int msa)

		/* Restore the scalar FP control & status register */
		if (!was_fpu_owner)
		asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31));
		write_32bit_cp1_register(CP1_STATUS,
		current->thread.fpu.fcr31);
		}

		out:

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