drm/armada: clear plane enable bit when disabling (d76dcc72) · Commits · 戴 / test

drivers/gpu/drm/armada/armada_crtc.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -1128,7 +1128,7 @@ int armada_drm_plane_disable(struct drm_plane *plane,
		{
		struct armada_plane *dplane = drm_to_armada_plane(plane);
		struct armada_crtc *dcrtc;
		u32 sram_para1, dma_ctrl0_mask;
		u32 sram_para1, enable_mask;

		if (!plane->crtc)
		return 0;
		@@ -1147,13 +1147,15 @@ int armada_drm_plane_disable(struct drm_plane *plane,
		if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
		sram_para1 = CFG_PDWN256x32 \| CFG_PDWN256x24 \| CFG_PDWN256x8 \|
		CFG_PDWN32x32 \| CFG_PDWN64x66;
		dma_ctrl0_mask = CFG_GRA_ENA;
		enable_mask = CFG_GRA_ENA;
		} else {
		/* Power down the Y/U/V FIFOs */
		sram_para1 = CFG_PDWN16x66 \| CFG_PDWN32x66;
		dma_ctrl0_mask = CFG_DMA_ENA;
		enable_mask = CFG_DMA_ENA;
		}

		dplane->state.ctrl0 &= ~enable_mask;

		dcrtc = drm_to_armada_crtc(plane->crtc);

		/* Wait for any preceding work to complete, but don't wedge */
		@@ -1161,7 +1163,7 @@ int armada_drm_plane_disable(struct drm_plane *plane,
		armada_drm_plane_work_cancel(dcrtc, dplane);

		spin_lock_irq(&dcrtc->irq_lock);
		armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
		armada_updatel(0, enable_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
		spin_unlock_irq(&dcrtc->irq_lock);

		armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);

+0 −2

Original line number	Diff line number	Diff line
		@@ -270,8 +270,6 @@ static int armada_ovl_plane_disable(struct drm_plane *plane,
		if (dplane->base.base.crtc)
		drm_to_armada_crtc(dplane->base.base.crtc)->plane = NULL;

		dplane->base.state.ctrl0 = 0;

		fb = xchg(&dplane->old_fb, NULL);
		if (fb)
		drm_framebuffer_put(fb);