Commit d749d94b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-4.4/devicetree' of http://github.com/Broadcom/stblinux into next/dt 

Merge "Broadcom devicetree changes for v4.4" from Florian Fainelli:

This pull requests contains the following Broadcom SoCs Device Tree changes:

- Brian Norris documents the BCM7445 SoCs Power Management controllers and
  hardware and updates the reference BCM7445 Device Tree with these nodes

- Florian Fainelli documents the BCM7xxx write-pairing feature in the top-level
  BCM7xxx binding document

- Hauke Merthens enables the NAND controller for the Asus RT-AC87U and adds the
  GPIO pin controlling the USB power supply on Netgear R6250

- Jon Mason adds support for the NorthStar Plus SoC by providing a top-level
  binding document and the minimalist device tree skeleton for these SoCs

- Rafal Milecki adds support for the Netgear R7000 (BCM5301x SoC)

- Ray Jui provides a set of Cygnus DT changes that make the Device Tree clearer
  and more correct with respect to how the hardware is designed. He also enables
  the NAND controller on the bcm911360_entphn design, enables a bunch of
  peripherals on the bcm958305k evaluation board, and adds a skeleton .dtsi file
  for the touchscreen extansion board(s)

* tag 'arm-soc/for-4.4/devicetree' of http://github.com/Broadcom/stblinux:
  ARM: dts: move aliases back to .dts in Cygnus
  ARM: dts: fix Cygnus nand device node
  ARM: dts: enable touchscreen support on Cygnus
  ARM: dts: Enable NAND support on bcm911360_entphn
  ARM: dts: Enable various peripherals on bcm958305k
  ARM: dts: Reorder Cygnus peripherals
  ARM: dts: Move all Cygnus peripherals into axi bus
  ARM: dts: Put Cygnus core components under core bus
  ARM: dts: Use label for device nodes in Cygnus dts
  ARM: dts: consolidate aliases for Cygnus dt files
  ARM: BCM5301X: Netgear R6250 add USB GPIO
  Documentation: bindings: brcmstb: Document write-pairing
  ARM: dts: brcmstb: add BCM7445 system PM DT nodes
  Documentation: dt: brcmstb: add system PM bindings
  ARM: BCM5301X: add NAND flash chip description for Asus RT-AC87U
  ARM: BCM5301X: Add DT for Netgear R7000
  ARM: NSP: add minimal Northstar Plus device tree
  dt-bindings: Create Documentation for NSP DT bindings
parents d27199cb eef228e3

Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt

+160 −2
Original line number Diff line number Diff line
@@ -20,6 +20,25 @@ system control is required: 
    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"

    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"



hif-cpubiuctrl node

-------------------

SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit

(BIU) block which controls and interfaces the CPU complex to the different

Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block

offers a feature called Write Pairing which consists in collapsing two adjacent

cache lines into a single (bursted) write transaction towards the memory

controller (MEMC) to maximize write bandwidth.



Required properties:



    - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"



Optional properties:



    - brcm,write-pairing:

	Boolean property, which when present indicates that the chip

	supports write-pairing.



example:

    rdb {

        #address-cells = <1>;
@@ -35,6 +54,7 @@ example: 
        hif_cpubiuctrl: syscon@3e2400 {

            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";

            reg = <0x3e2400 0x5b4>;

            brcm,write-pairing;

        };



        hif_continuation: syscon@452000 {
@@ -43,8 +63,7 @@ example: 
        };

    };



Lastly, nodes that allow for support of SMP initialization and reboot are

required:

Nodes that allow for support of SMP initialization and reboot are required:



smpboot

-------
@@ -95,3 +114,142 @@ example: 
        compatible = "brcm,brcmstb-reboot";

        syscon = <&sun_top_ctrl 0x304 0x308>;

    };







Power management

----------------



For power management (particularly, S2/S3/S5 system suspend), the following SoC

components are needed:



= Always-On control block (AON CTRL)



This hardware provides control registers for the "always-on" (even in low-power

modes) hardware, such as the Power Management State Machine (PMSM).



Required properties:

- compatible     : should contain "brcm,brcmstb-aon-ctrl"

- reg            : the register start and length for the AON CTRL block



Example:



aon-ctrl@410000 {

	compatible = "brcm,brcmstb-aon-ctrl";

	reg = <0x410000 0x400>;

};



= Memory controllers



A Broadcom STB SoC typically has a number of independent memory controllers,

each of which may have several associated hardware blocks, which are versioned

independently (control registers, DDR PHYs, etc.). One might consider

describing these controllers as a parent "memory controllers" block, which

contains N sub-nodes (one for each controller in the system), each of which is

associated with a number of hardware register resources (e.g., its PHY). See

the example device tree snippet below.



== MEMC (MEMory Controller)



Represents a single memory controller instance.



Required properties:

- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"



Should contain subnodes for any of the following relevant hardware resources:



== DDR PHY control



Control registers for this memory controller's DDR PHY.



Required properties:

- compatible     : should contain one of these

	"brcm,brcmstb-ddr-phy-v225.1"

	"brcm,brcmstb-ddr-phy-v240.1"

	"brcm,brcmstb-ddr-phy-v240.2"



- reg            : the DDR PHY register range



== DDR SHIMPHY



Control registers for this memory controller's DDR SHIMPHY.



Required properties:

- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"

- reg            : the DDR SHIMPHY register range



== MEMC DDR control



Sequencer DRAM parameters and control registers. Used for Self-Refresh

Power-Down (SRPD), among other things.



Required properties:

- compatible     : should contain "brcm,brcmstb-memc-ddr"

- reg            : the MEMC DDR register range



Example:



memory_controllers {

	ranges;

	compatible = "simple-bus";



	memc@0 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1106000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1106000 0x21c>;

		};



		shimphy@f1108000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1108000 0xe4>;

		};



		memc-ddr@f1102000 {

			reg = <0xf1102000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};



	memc@1 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1186000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1186000 0x21c>;

		};



		shimphy@f1188000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1188000 0xe4>;

		};



		memc-ddr@f1182000 {

			reg = <0xf1182000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};



	memc@2 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1206000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1206000 0x21c>;

		};



		shimphy@f1208000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1208000 0xe4>;

		};



		memc-ddr@f1202000 {

			reg = <0xf1202000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};

};

Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt

0 → 100644
+34 −0
Original line number Diff line number Diff line 
Broadcom Northstar Plus device tree bindings

--------------------------------------------



Broadcom Northstar Plus family of SoCs are used for switching control

and management applications as well as residential router/gateway

applications. The SoC features dual core Cortex A9 ARM CPUs, integrating

several peripheral interfaces including multiple Gigabit Ethernet PHYs,

DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,

SATA and several other IO controllers.



Boards with Northstar Plus SoCs shall have the following properties:



Required root node property:



BCM58522

compatible = "brcm,bcm58522", "brcm,nsp";



BCM58525

compatible = "brcm,bcm58525", "brcm,nsp";



BCM58535

compatible = "brcm,bcm58535", "brcm,nsp";



BCM58622

compatible = "brcm,bcm58622", "brcm,nsp";



BCM58623

compatible = "brcm,bcm58623", "brcm,nsp";



BCM58625

compatible = "brcm,bcm58625", "brcm,nsp";



BCM88312

compatible = "brcm,bcm88312", "brcm,nsp";

arch/arm/boot/dts/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ 
	bcm47081-buffalo-wzr-900dhp.dtb \

	bcm4709-asus-rt-ac87u.dtb \

	bcm4709-buffalo-wxr-1900dhp.dtb \

	bcm4709-netgear-r7000.dtb \

	bcm4709-netgear-r8000.dtb

dtb-$(CONFIG_ARCH_BCM_63XX) += \

	bcm963138dvt.dtb
@@ -83,6 +84,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ 
dtb-$(CONFIG_ARCH_BCM_MOBILE) += \

	bcm28155-ap.dtb \

	bcm21664-garnet.dtb

dtb-$(CONFIG_ARCH_BCM_NSP) += \

	bcm958625k.dtb

dtb-$(CONFIG_ARCH_BERLIN) += \

	berlin2-sony-nsz-gs7.dtb \

	berlin2cd-google-chromecast.dtb \

arch/arm/boot/dts/bcm-cygnus.dtsi

+175 −159
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 


#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/clock/bcm-cygnus.h>



#include "skeleton.dtsi"
@@ -54,6 +55,42 @@ 


	/include/ "bcm-cygnus-clock.dtsi"



	core {

		compatible = "simple-bus";

		ranges = <0x00000000 0x19000000 0x1000000>;

		#address-cells = <1>;

		#size-cells = <1>;



		timer@20200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x20200 0x100>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&periph_clk>;

		};



		gic: interrupt-controller@21000 {

			compatible = "arm,cortex-a9-gic";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x21000 0x1000>,

			      <0x20100 0x100>;

		};



		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0x22000 0x1000>;

			cache-unified;

			cache-level = <2>;

		};

	};



	axi {

		compatible = "simple-bus";

		ranges;

		#address-cells = <1>;

		#size-cells = <1>;



		pinctrl: pinctrl@0x0301d0c8 {

			compatible = "brcm,cygnus-pinmux";

			reg = <0x0301d0c8 0x30>,
@@ -68,52 +105,32 @@ 
			gpio-controller;

		};



	gpio_ccm: gpio@1800a000 {

		compatible = "brcm,cygnus-ccm-gpio";

		reg = <0x1800a000 0x50>,

		      <0x0301d164 0x20>;

		#gpio-cells = <2>;

		gpio-controller;

		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

	};



	gpio_asiu: gpio@180a5000 {

		compatible = "brcm,cygnus-asiu-gpio";

		reg = <0x180a5000 0x668>;

		#gpio-cells = <2>;

		gpio-controller;



		pinmux = <&pinctrl>;



		interrupt-controller;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

	};



	amba {

		i2c0: i2c@18008000 {

			compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";

			reg = <0x18008000 0x100>;

			#address-cells = <1>;

		#size-cells = <1>;

		compatible = "arm,amba-bus", "simple-bus";

		interrupt-parent = <&gic>;

		ranges;

			#size-cells = <0>;

			interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;

			clock-frequency = <100000>;

			status = "disabled";

		};



		wdt@18009000 {

		wdt0: wdt@18009000 {

			compatible = "arm,sp805" , "arm,primecell";

			reg = <0x18009000 0x1000>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&axi81_clk>;

			clock-names = "apb_pclk";

		};

	};



	i2c0: i2c@18008000 {

		compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";

		reg = <0x18008000 0x100>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;

		clock-frequency = <100000>;

		status = "disabled";

		gpio_ccm: gpio@1800a000 {

			compatible = "brcm,cygnus-ccm-gpio";

			reg = <0x1800a000 0x50>,

			      <0x0301d164 0x20>;

			#gpio-cells = <2>;

			gpio-controller;

			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

		};



		i2c1: i2c@1800b000 {
@@ -213,8 +230,9 @@ 
		};



		nand: nand@18046000 {

		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";

		reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>;

			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";

			reg = <0x18046000 0x600>, <0xf8105408 0x600>,

			      <0x18046f00 0x20>;

			reg-names = "nand", "iproc-idm", "iproc-ext";

			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -224,27 +242,25 @@ 
			brcm,nand-has-wp;

		};



	gic: interrupt-controller@19021000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		gpio_asiu: gpio@180a5000 {

			compatible = "brcm,cygnus-asiu-gpio";

			reg = <0x180a5000 0x668>;

			#gpio-cells = <2>;

			gpio-controller;



			pinmux = <&pinctrl>;



			interrupt-controller;

		reg = <0x19021000 0x1000>,

		      <0x19020100 0x100>;

			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		};



	L2: l2-cache {

		compatible = "arm,pl310-cache";

		reg = <0x19022000 0x1000>;

		cache-unified;

		cache-level = <2>;

		touchscreen: tsc@180a6000 {

			compatible = "brcm,iproc-touchscreen";

			reg = <0x180a6000 0x40>;

			clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;

			clock-names = "tsc_clk";

			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



	timer@19020200 {

		compatible = "arm,cortex-a9-global-timer";

		reg = <0x19020200 0x100>;

		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&periph_clk>;

	};



};

arch/arm/boot/dts/bcm-nsp.dtsi

0 → 100644
+119 −0
Original line number Diff line number Diff line 
/*

 *  BSD LICENSE

 *

 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.

 *

 *  Redistribution and use in source and binary forms, with or without

 *  modification, are permitted provided that the following conditions

 *  are met:

 *

 *    * Redistributions of source code must retain the above copyright

 *      notice, this list of conditions and the following disclaimer.

 *    * Redistributions in binary form must reproduce the above copyright

 *      notice, this list of conditions and the following disclaimer in

 *      the documentation and/or other materials provided with the

 *      distribution.

 *    * Neither the name of Broadcom Corporation nor the names of its

 *      contributors may be used to endorse or promote products derived

 *      from this software without specific prior written permission.

 *

 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>



#include "skeleton.dtsi"



/ {

	compatible = "brcm,nsp";

	model = "Broadcom Northstar Plus SoC";

	interrupt-parent = <&gic>;



	mpcore {

		compatible = "simple-bus";

		ranges = <0x00000000 0x19020000 0x00003000>;

		#address-cells = <1>;

		#size-cells = <1>;



		cpus {

			#address-cells = <1>;

			#size-cells = <0>;



			cpu@0 {

				device_type = "cpu";

				compatible = "arm,cortex-a9";

				next-level-cache = <&L2>;

				reg = <0x0>;

			};

		};



		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0x2000 0x1000>;

			cache-unified;

			cache-level = <2>;

		};



		gic: interrupt-controller@19021000 {

			compatible = "arm,cortex-a9-gic";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x1000 0x1000>,

			      <0x0100 0x100>;

		};



		timer@19020200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x0200 0x100>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&periph_clk>;

		};

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		periph_clk: periph_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <500000000>;

		};

	};



	axi {

		compatible = "simple-bus";

		ranges = <0x00000000 0x18000000 0x00001000>;

		#address-cells = <1>;

		#size-cells = <1>;



		uart0: serial@18000300 {

			compatible = "ns16550a";

			reg = <0x0300 0x100>;

			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			clock-frequency = <62499840>;

			status = "disabled";

		};



		uart1: serial@18000400 {

			compatible = "ns16550a";

			reg = <0x0400 0x100>;

			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			clock-frequency = <62499840>;

			status = "disabled";

		};

	};

};

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