Commit d727be7b authored Apr 02, 2020 by Atish Patra Committed by Marc Zyngier Apr 17, 2020

irqchip/sifive-plic: Fix maximum priority threshold value

As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.

Fixes: ccbe80ba ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200403014609.71831-1-atish.patra@wdc.com

parent 3688b0db

drivers/irqchip/irq-sifive-plic.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -56,7 +56,7 @@
		#define CONTEXT_THRESHOLD 0x00
		#define CONTEXT_CLAIM 0x04

		#define PLIC_DISABLE_THRESHOLD 0xf
		#define PLIC_DISABLE_THRESHOLD 0x7
		#define PLIC_ENABLE_THRESHOLD 0

		struct plic_priv {