Commit d725cf38 authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle
Browse files

[MIPS] MT: Reenable EIC support and add support for SOCit SC. 



Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ef300e42

arch/mips/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -1557,6 +1557,7 @@ config MIPS_MT_SMP 
	bool "Use 1 TC on each available VPE for SMP"

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select CPU_MIPSR2_SRS

	select MIPS_MT

	select NR_CPUS_DEFAULT_2
@@ -1572,6 +1573,7 @@ config MIPS_MT_SMTC 
	#depends on CPU_MIPS64_R2		# once there is hardware ...

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select CPU_MIPSR2_SRS

	select MIPS_MT

	select NR_CPUS_DEFAULT_8
@@ -1584,6 +1586,8 @@ config MIPS_MT_SMTC 
config MIPS_VPE_LOADER

	bool "VPE loader support."

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select MIPS_MT

	help

	  Includes a loader for loading an elf relocatable object

arch/mips/kernel/irq-msc01.c

+5 −5
Original line number Diff line number Diff line
@@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = { 
};





void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)

void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)

{

	extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);



	_icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);

	_icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);



	/* Reset interrupt controller - initialises all registers to 0 */

	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
@@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) 


		switch (imp->im_type) {

		case MSC01_IRQ_EDGE:

			set_irq_chip(base+n, &msc_edgeirq_type);

			set_irq_chip(irqbase+n, &msc_edgeirq_type);

			if (cpu_has_veic)

				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);

			else

				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);

			break;

		case MSC01_IRQ_LEVEL:

			set_irq_chip(base+n, &msc_levelirq_type);

			set_irq_chip(irqbase+n, &msc_levelirq_type);

			if (cpu_has_veic)

				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);

			else
@@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) 
		}

	}



	irq_base = base;

	irq_base = irqbase;



	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */

arch/mips/mips-boards/malta/malta_int.c

+13 −8
Original line number Diff line number Diff line
@@ -311,16 +311,21 @@ void __init arch_init_irq(void) 
	if (!cpu_has_veic)

		mips_cpu_irq_init();



        switch(mips_revision_corid) {

        case MIPS_REVISION_CORID_CORE_MSC:

        case MIPS_REVISION_CORID_CORE_FPGA2:

        case MIPS_REVISION_CORID_CORE_FPGA3:

        case MIPS_REVISION_CORID_CORE_24K:

        case MIPS_REVISION_CORID_CORE_EMUL_MSC:

        switch(mips_revision_sconid) {

        case MIPS_REVISION_SCON_SOCIT:

        case MIPS_REVISION_SCON_ROCIT:

		if (cpu_has_veic)

			init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);

		else

			init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);

		break;



        case MIPS_REVISION_SCON_SOCITSC:

        case MIPS_REVISION_SCON_SOCITSCP:

		if (cpu_has_veic)

			init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);

			init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);

		else

			init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);

			init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);

	}



	if (cpu_has_veic) {

include/asm-mips/mips-boards/malta.h

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ 
#include <asm/mips-boards/msc01_pci.h>

#include <asm/gt64120.h>



/* Mips interrupt controller found in SOCit variations */

#define MIPS_MSC01_IC_REG_BASE		0x1bc40000

#define MIPS_SOCITSC_IC_REG_BASE	0x1ffa0000



/*

 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics

 * Bonito system controllers.

include/asm-mips/msc01_ic.h

+1 −4
Original line number Diff line number Diff line
@@ -94,10 +94,7 @@ 
/*

 * MIPS System controller interrupt register base.

 *

 * FIXME - are these macros specific to Malta and co or to the MSC?  If the

 * latter, they should be moved elsewhere.

 */

#define MIPS_MSC01_IC_REG_BASE	0x1bc40000



/*****************************************************************************

 * Absolute register addresses
@@ -144,7 +141,7 @@ typedef struct msc_irqmap { 
#define MSC01_IRQ_LEVEL		0

#define MSC01_IRQ_EDGE		1



extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);

extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);

extern void ll_msc_irq(void);



#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */

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