Commit d718d79e authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/panel: simple: Add support for AUO B080UAN01 



The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four
DSI lanes. It can be supported by the simple-panel driver.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d901d2ba

Documentation/devicetree/bindings/panel/auo,b080uan01.txt

0 → 100644
+7 −0
Original line number Diff line number Diff line 
AU Optronics Corporation 8.0" WUXGA TFT LCD panel



Required properties:

- compatible: should be "auo,b101ean01"



This binding is compatible with the simple-panel binding, which is specified

in simple-panel.txt in this directory.

drivers/gpu/drm/panel/panel-simple.c

+31 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,34 @@ struct panel_desc_dsi { 
	unsigned int lanes;

};



static const struct drm_display_mode auo_b080uan01_mode = {

	.clock = 154500,

	.hdisplay = 1200,

	.hsync_start = 1200 + 62,

	.hsync_end = 1200 + 62 + 4,

	.htotal = 1200 + 62 + 4 + 62,

	.vdisplay = 1920,

	.vsync_start = 1920 + 9,

	.vsync_end = 1920 + 9 + 2,

	.vtotal = 1920 + 9 + 2 + 8,

	.vrefresh = 60,

};



static const struct panel_desc_dsi auo_b080uan01 = {

	.desc = {

		.modes = &auo_b080uan01_mode,

		.num_modes = 1,

		.bpc = 8,

		.size = {

			.width = 108,

			.height = 272,

		},

	},

	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,

	.format = MIPI_DSI_FMT_RGB888,

	.lanes = 4,

};



static const struct drm_display_mode lg_ld070wx3_sl01_mode = {

	.clock = 71000,

	.hdisplay = 800,
@@ -1262,6 +1290,9 @@ static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 


static const struct of_device_id dsi_of_match[] = {

	{

		.compatible = "auo,b080uan01",

		.data = &auo_b080uan01

	}, {

		.compatible = "lg,ld070wx3-sl01",

		.data = &lg_ld070wx3_sl01

	}, {

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