drm/tegra: dc: Describe register copies (d700ba7a) · Commits · 戴 / test

Most of the display controller's registers are double-buffered, a few of them are triple-buffered. The ASSEMBLY shadow copy is latched intto the ACTIVE copy for double-buffered registers. For triple-buffered registers the ASSEMBLY copy is first latched into the ARM copy. Latching into the ACTIVE copy happens immediately if the controller is inactive. Otherwise the latching happens on the next frame boundary. The latching of the ASSEMBLY into the ARM copy happens immediately. Latching is controlled by a set of *_ACT_REQ and *_UPDATE bits in the DC_CMD_STATE_CONTROL register. Signed-off-by:

Thierry Reding <treding@nvidia.com>

drivers/gpu/drm/tegra/dc.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -53,6 +53,18 @@ static void tegra_dc_cursor_commit(struct tegra_dc *dc)
		tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
		}

		/*
		* Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
		* *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
		* Latching happens mmediately if the display controller is in STOP mode or
		* on the next frame boundary otherwise.
		*
		* Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
		* ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
		* are written. When the *_ACT_REQ bits are written, the ARM copy is latched
		* into the ACTIVE copy, either immediately if the display controller is in
		* STOP mode, or at the next frame boundary otherwise.
		*/
		static void tegra_dc_commit(struct tegra_dc *dc)
		{
		tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);

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