drm/amd/powerplay: support Vega10 retrieving and setting ppfeatures (d6e40301) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+101 −0

Original line number	Diff line number	Diff line
		@@ -4323,6 +4323,105 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
		return result;
		}

		static int vega10_get_ppfeature_status(struct pp_hwmgr hwmgr, char buf)
		{
		static const char *ppfeature_name[] = {
		"DPM_PREFETCHER",
		"GFXCLK_DPM",
		"UCLK_DPM",
		"SOCCLK_DPM",
		"UVD_DPM",
		"VCE_DPM",
		"ULV",
		"MP0CLK_DPM",
		"LINK_DPM",
		"DCEFCLK_DPM",
		"AVFS",
		"GFXCLK_DS",
		"SOCCLK_DS",
		"LCLK_DS",
		"PPT",
		"TDC",
		"THERMAL",
		"GFX_PER_CU_CG",
		"RM",
		"DCEFCLK_DS",
		"ACDC",
		"VR0HOT",
		"VR1HOT",
		"FW_CTF",
		"LED_DISPLAY",
		"FAN_CONTROL",
		"FAST_PPT",
		"DIDT",
		"ACG",
		"PCC_LIMIT"};
		static const char *output_title[] = {
		"FEATURES",
		"BITMASK",
		"ENABLEMENT"};
		uint64_t features_enabled;
		int i;
		int ret = 0;
		int size = 0;

		ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
		PP_ASSERT_WITH_CODE(!ret,
		"[EnableAllSmuFeatures] Failed to get enabled smc features!",
		return ret);

		size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
		size += sprintf(buf + size, "%-19s %-22s %s\n",
		output_title[0],
		output_title[1],
		output_title[2]);
		for (i = 0; i < GNLD_FEATURES_MAX; i++) {
		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
		ppfeature_name[i],
		1ULL << i,
		(features_enabled & (1ULL << i)) ? "Y" : "N");
		}

		return size;
		}

		static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
		{
		uint64_t features_enabled;
		uint64_t features_to_enable;
		uint64_t features_to_disable;
		int ret = 0;

		if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
		return -EINVAL;

		ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
		if (ret)
		return ret;

		features_to_disable =
		(features_enabled ^ new_ppfeature_masks) & features_enabled;
		features_to_enable =
		(features_enabled ^ new_ppfeature_masks) ^ features_to_disable;

		pr_debug("features_to_disable 0x%llx\n", features_to_disable);
		pr_debug("features_to_enable 0x%llx\n", features_to_enable);

		if (features_to_disable) {
		ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
		if (ret)
		return ret;
		}

		if (features_to_enable) {
		ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
		if (ret)
		return ret;
		}

		return 0;
		}

		static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
		enum pp_clock_type type, char *buf)
		{
		@@ -5068,6 +5167,8 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
		.get_asic_baco_state = vega10_baco_get_state,
		.set_asic_baco_state = vega10_baco_set_state,
		.enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
		.get_ppfeature_status = vega10_get_ppfeature_status,
		.set_ppfeature_status = vega10_set_ppfeature_status,
		};

		int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)

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