Commit d6e055e8 authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
Browse files

PCI: Add constant PCI_STATUS_ERROR_BITS 



This collection of PCI error bits is used in more than one driver,
so move it to the PCI core.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 90760b21

drivers/net/ethernet/marvell/skge.h

+0 −7
Original line number Diff line number Diff line
@@ -15,13 +15,6 @@ 
#define  PCI_VPD_ROM_SZ	7L<<14	/* VPD ROM size 0=256, 1=512, ... */

#define  PCI_REV_DESC	1<<2	/* Reverse Descriptor bytes */



#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \

			       PCI_STATUS_SIG_SYSTEM_ERROR | \

			       PCI_STATUS_REC_MASTER_ABORT | \

			       PCI_STATUS_REC_TARGET_ABORT | \

			       PCI_STATUS_SIG_TARGET_ABORT | \

			       PCI_STATUS_PARITY)



enum csr_regs {

	B0_RAP	= 0x0000,

	B0_CTST	= 0x0004,

drivers/net/ethernet/marvell/sky2.h

+0 −7
Original line number Diff line number Diff line
@@ -252,13 +252,6 @@ enum { 
};





#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \

			       PCI_STATUS_SIG_SYSTEM_ERROR | \

			       PCI_STATUS_REC_MASTER_ABORT | \

			       PCI_STATUS_REC_TARGET_ABORT | \

			       PCI_STATUS_SIG_TARGET_ABORT | \

			       PCI_STATUS_PARITY)



enum csr_regs {

	B0_RAP		= 0x0000,

	B0_CTST		= 0x0004,

include/linux/pci.h

+7 −0
Original line number Diff line number Diff line
@@ -42,6 +42,13 @@ 


#include <linux/pci_ids.h>



#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY  | \

			       PCI_STATUS_SIG_SYSTEM_ERROR | \

			       PCI_STATUS_REC_MASTER_ABORT | \

			       PCI_STATUS_REC_TARGET_ABORT | \

			       PCI_STATUS_SIG_TARGET_ABORT | \

			       PCI_STATUS_PARITY)



/*

 * The PCI interface treats multi-function devices as independent

 * devices.  The slot/function address of each device is encoded

CRA Git | Maintained and supported by SUSTech CRA and CCSE