Commit d6dd735f authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Olof Johansson
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arm: socfpga: Add SMP support for actual socfpga harware 



Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Signed-off-by: default avatarPavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent c08e20d2

Documentation/devicetree/bindings/arm/altera/socfpga-system.txt

+2 −0
Original line number Diff line number Diff line
@@ -3,9 +3,11 @@ Altera SOCFPGA System Manager 
Required properties:

- compatible : "altr,sys-mgr"

- reg : Should contain 1 register ranges(address and length)

- cpu1-start-addr : CPU1 start address in hex.



Example:

	 sysmgr@ffd08000 {

		compatible = "altr,sys-mgr";

		reg = <0xffd08000 0x1000>;

		cpu1-start-addr = <0xffd080c4>;

	};

arch/arm/boot/dts/socfpga_cyclone5.dts

+4 −0
Original line number Diff line number Diff line
@@ -56,5 +56,9 @@ 
		serial1@ffc03000 {

			clock-frequency = <100000000>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd080c4>;

		};

	};

};

arch/arm/boot/dts/socfpga_vt.dts

+4 −0
Original line number Diff line number Diff line
@@ -56,5 +56,9 @@ 
		serial1@ffc03000 {

			clock-frequency = <7372800>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd08010>;

		};

	};

};

arch/arm/mach-socfpga/core.h

+3 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
#ifndef __MACH_CORE_H

#define __MACH_CORE_H



extern void secondary_startup(void);

extern void socfpga_secondary_startup(void);

extern void __iomem *socfpga_scu_base_addr;



extern void socfpga_init_clocks(void);
@@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void); 
extern struct smp_operations socfpga_smp_ops;

extern char secondary_trampoline, secondary_trampoline_end;



extern unsigned long cpu1start_addr;



#define SOCFPGA_SCU_VIRT_BASE   0xfffec000



#endif

arch/arm/mach-socfpga/headsmp.S

+12 −4
Original line number Diff line number Diff line
@@ -13,13 +13,21 @@ 
	__CPUINIT

	.arch	armv7-a



#define CPU1_START_ADDR 	        0xffd08010



ENTRY(secondary_trampoline)

	movw	r0, #:lower16:CPU1_START_ADDR

	movt  r0, #:upper16:CPU1_START_ADDR

	movw	r2, #:lower16:cpu1start_addr

	movt  r2, #:upper16:cpu1start_addr



	/* The socfpga VT cannot handle a 0xC0000000 page offset when loading

		the cpu1start_addr, we bit clear it. Tested on HW and VT. */

	bic	r2, r2, #0x40000000



	ldr	r0, [r2]

	ldr	r1, [r0]

	bx	r1



ENTRY(secondary_trampoline_end)



ENTRY(socfpga_secondary_startup)

       bl      v7_invalidate_l1

       b       secondary_startup

ENDPROC(socfpga_secondary_startup)

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