Commit d6666be6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd 

Pull MTD updates from Brian Norris:
 "Summary:
   - Add device tree support for DoC3

   - SPI NOR:
        Refactoring, for better layering between spi-nor.c and its
        driver users (e.g., m25p80.c)

        New flash device support

        Support 6-byte ID strings

   - NAND:
        New NAND driver for Allwinner SoC's (sunxi)

        GPMI NAND: add support for raw (no ECC) access, for testing
        purposes

        Add ATO manufacturer ID

        A few odd driver fixes

   - MTD tests:
        Allow testers to compensate for OOB bitflips in oobtest

        Fix a torturetest regression

   - nandsim: Support longer ID byte strings

  And more"

* tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd: (63 commits)
  mtd: tests: abort torturetest on erase errors
  mtd: physmap_of: fix potential NULL dereference
  mtd: spi-nor: allow NULL as chip name and try to auto detect it
  mtd: nand: gpmi: add raw oob access functions
  mtd: nand: gpmi: add proper raw access support
  mtd: nand: gpmi: add gpmi_copy_bits function
  mtd: spi-nor: factor out write_enable() for erase commands
  mtd: spi-nor: add support for s25fl128s
  mtd: spi-nor: remove the jedec_id/ext_id
  mtd: spi-nor: add id/id_len for flash_info{}
  mtd: nand: correct the comment of function nand_block_isreserved()
  jffs2: Drop bogus if in comment
  mtd: atmel_nand: replace memcpy32_toio/memcpy32_fromio with memcpy
  mtd: cafe_nand: drop duplicate .write_page implementation
  mtd: m25p80: Add support for serial flash Spansion S25FL132K
  MTD: m25p80: fix inconsistency in m25p_ids compared to spi_nor_ids
  mtd: spi-nor: improve wait-till-ready timeout loop
  mtd: delete unnecessary checks before two function calls
  mtd: nand: omap: Fix NAND enumeration on 3430 LDP
  mtd: nand: add ATO manufacturer info
  ...
parents 0ea90b9e 68f29815

Documentation/devicetree/bindings/mtd/atmel-nand.txt

+4 −2
Original line number Diff line number Diff line
@@ -5,7 +5,9 @@ Required properties: 
- reg : should specify localbus address and size used for the chip,

	and hardware ECC controller if available.

	If the hardware ECC is PMECC, it should contain address and size for

	PMECC, PMECC Error Location controller and ROM which has lookup tables.

	PMECC and PMECC Error Location controller.

	The PMECC lookup table address and size in ROM is optional. If not

	specified, driver will build it in runtime.

- atmel,nand-addr-offset : offset for the address latch.

- atmel,nand-cmd-offset : offset for the command latch.

- #address-cells, #size-cells : Must be present if the device has sub-nodes
@@ -27,7 +29,7 @@ Optional properties: 
  are: 512, 1024.

- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM

  for different sector size. First one is for sector size 512, the next is for

  sector size 1024.

  sector size 1024. If not specified, driver will build the table in runtime.

- nand-bus-width : 8 or 16 bus width if not present 8

- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false

- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash

Documentation/devicetree/bindings/mtd/diskonchip.txt

0 → 100644
+15 −0
Original line number Diff line number Diff line 
M-Systems and Sandisk DiskOnChip devices



M-System DiskOnChip G3

======================

The Sandisk (formerly M-Systems) docg3 is a nand device of 64M to 256MB.



Required properties:

 - compatible: should be "m-systems,diskonchip-g3"

 - reg: register base and size



Example:

	docg3: flash@0 {

		compatible = "m-systems,diskonchip-g3";

		reg = <0x0 0x2000>;

	};

Documentation/devicetree/bindings/mtd/gpio-control-nand.txt

+7 −7
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ Required properties: 
  are made in native endianness.

- #address-cells, #size-cells : Must be present if the device has sub-nodes

  representing partitions.

- gpios : specifies the gpio pins to control the NAND device.  nwp is an

  optional gpio and may be set to 0 if not present.

- gpios : Specifies the GPIO pins to control the NAND device.  The order of

  GPIO references is:  RDY, nCE, ALE, CLE, and an optional nWP.



Optional properties:

- bank-width : Width (in bytes) of the device.  If not present, the width
@@ -35,11 +35,11 @@ gpio-nand@1,0 { 
	reg = <1 0x0000 0x2>;

	#address-cells = <1>;

	#size-cells = <1>;

	gpios = <&banka 1 0	/* rdy */

		 &banka 2 0 	/* nce */

		 &banka 3 0 	/* ale */

		 &banka 4 0 	/* cle */

		 0		/* nwp */>;

	gpios = <&banka 1 0>,	/* RDY */

		<&banka 2 0>, 	/* nCE */

		<&banka 3 0>, 	/* ALE */

		<&banka 4 0>, 	/* CLE */

		<0>;		/* nWP */



	partition@0 {

	...

Documentation/devicetree/bindings/mtd/sunxi-nand.txt

0 → 100644
+45 −0
Original line number Diff line number Diff line 
Allwinner NAND Flash Controller (NFC)



Required properties:

- compatible : "allwinner,sun4i-a10-nand".

- reg : shall contain registers location and length for data and reg.

- interrupts : shall define the nand controller interrupt.

- #address-cells: shall be set to 1. Encode the nand CS.

- #size-cells : shall be set to 0.

- clocks : shall reference nand controller clocks.

- clock-names : nand controller internal clock names. Shall contain :

    * "ahb" : AHB gating clock

    * "mod" : nand controller clock



Optional children nodes:

Children nodes represent the available nand chips.



Optional properties:

- allwinner,rb : shall contain the native Ready/Busy ids.

 or

- rb-gpios : shall contain the gpios used as R/B pins.

- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",

  "soft_bch" or "none")



see Documentation/devicetree/mtd/nand.txt for generic bindings.





Examples:

nfc: nand@01c03000 {

	compatible = "allwinner,sun4i-a10-nand";

	reg = <0x01c03000 0x1000>;

	interrupts = <0 37 1>;

	clocks = <&ahb_gates 13>, <&nand_clk>;

	clock-names = "ahb", "mod";

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;

	status = "okay";



	nand@0 {

		reg = <0>;

		allwinner,rb = <0>;

		nand-ecc-mode = "soft_bch";

	};

};

drivers/memory/fsl_ifc.c

+11 −2
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ int fsl_ifc_find(phys_addr_t addr_base) 
	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)

		return -ENODEV;



	for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {

	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {

		u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);

		if (cspr & CSPR_V && (cspr & CSPR_BA) ==

				convert_ifc_address(addr_base))
@@ -213,7 +213,7 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data) 
static int fsl_ifc_ctrl_probe(struct platform_device *dev)

{

	int ret = 0;



	int version, banks;



	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
@@ -231,6 +231,15 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev) 
		goto err;

	}



	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &

			FSL_IFC_VERSION_MASK;

	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;

	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",

		version >> 24, (version >> 16) & 0xf, banks);



	fsl_ifc_ctrl_dev->version = version;

	fsl_ifc_ctrl_dev->banks = banks;



	/* get the Controller level irq */

	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);

	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {

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