arm64: zynqmp: Add support for Xilinx zc12XX boards (d665c743) · Commits · 戴 / test

Documentation/devicetree/bindings/arm/xilinx.txt

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		@@ -19,6 +19,15 @@ Required root node properties:

		Additional compatible strings:

		- Xilinx internal board zc1232
		"xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"

		- Xilinx internal board zc1254
		"xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"

		- Xilinx internal board zc1275
		"xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"

		- Xilinx 96boards compatible board zcu100
		"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"

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		# SPDX-License-Identifier: GPL-2.0
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
		dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb

0 → 100644

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		// SPDX-License-Identifier: GPL-2.0+
		/*
		* dts file for Xilinx ZynqMP ZC1232
		*
		* (C) Copyright 2017 - 2018, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		*/

		/dts-v1/;

		#include "zynqmp.dtsi"
		#include "zynqmp-clk.dtsi"

		/ {
		model = "ZynqMP ZC1232 RevA";
		compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";

		aliases {
		serial0 = &uart0;
		serial1 = &dcc;
		};

		chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
		};

		memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
		};
		};

		&dcc {
		status = "okay";
		};

		&sata {
		status = "okay";
		/* SATA OOB timing settings */
		ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
		ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
		ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
		ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
		ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
		ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
		ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
		ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
		};

		&uart0 {
		status = "okay";
		};

0 → 100644

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		// SPDX-License-Identifier: GPL-2.0+
		/*
		* dts file for Xilinx ZynqMP ZC1254
		*
		* (C) Copyright 2015 - 2018, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
		*/

		/dts-v1/;

		#include "zynqmp.dtsi"
		#include "zynqmp-clk.dtsi"

		/ {
		model = "ZynqMP ZC1254 RevA";
		compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";

		aliases {
		serial0 = &uart0;
		serial1 = &dcc;
		};

		chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
		};

		memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
		};
		};

		&dcc {
		status = "okay";
		};

		&uart0 {
		status = "okay";
		};

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		// SPDX-License-Identifier: GPL-2.0+
		/*
		* dts file for Xilinx ZynqMP ZC1275
		*
		* (C) Copyright 2017 - 2018, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
		*/

		/dts-v1/;

		#include "zynqmp.dtsi"
		#include "zynqmp-clk.dtsi"

		/ {
		model = "ZynqMP ZC1275 RevA";
		compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";

		aliases {
		serial0 = &uart0;
		serial1 = &dcc;
		};

		chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
		};

		memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
		};
		};

		&dcc {
		status = "okay";
		};

		&uart0 {
		status = "okay";
		};