Commit d6622d91 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull late arm64 fixes from Will Deacon:
 "Three small arm64 fixes for 5.0.

  They fix a build breakage with clang introduced in 4.20, an oversight
  in our sigframe restoration relating to the SSBS bit and a boot fix
  for systems with newer revisions of our interrupt controller.

  Summary:

   - Fix handling of PSTATE.SSBS bit in sigreturn()

   - Fix version checking of the GIC during early boot

   - Fix clang builds failing due to use of NEON in the crypto code"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Relax GIC version check during early boot
  arm64/neon: Disable -Wincompatible-pointer-types when building with Clang
  arm64: fix SSBS sanitization
parents 7c903253 74698f69

arch/arm64/include/asm/neon-intrinsics.h

+4 −0
Original line number Diff line number Diff line
@@ -36,4 +36,8 @@ 
#include <arm_neon.h>

#endif



#ifdef CONFIG_CC_IS_CLANG

#pragma clang diagnostic ignored "-Wincompatible-pointer-types"

#endif



#endif /* __ASM_NEON_INTRINSICS_H */

arch/arm64/kernel/head.S

+1 −2
Original line number Diff line number Diff line
@@ -539,8 +539,7 @@ set_hcr: 
	/* GICv3 system register access */

	mrs	x0, id_aa64pfr0_el1

	ubfx	x0, x0, #24, #4

	cmp	x0, #1

	b.ne	3f

	cbz	x0, 3f



	mrs_s	x0, SYS_ICC_SRE_EL2

	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1

arch/arm64/kernel/ptrace.c

+8 −7
Original line number Diff line number Diff line
@@ -1702,19 +1702,20 @@ void syscall_trace_exit(struct pt_regs *regs) 
}



/*

 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487C.a

 * We also take into account DIT (bit 24), which is not yet documented, and

 * treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may be

 * allocated an EL0 meaning in future.

 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a.

 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is

 * not described in ARM DDI 0487D.a.

 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may

 * be allocated an EL0 meaning in future.

 * Userspace cannot use these until they have an architectural meaning.

 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format.

 * We also reserve IL for the kernel; SS is handled dynamically.

 */

#define SPSR_EL1_AARCH64_RES0_BITS \

	(GENMASK_ULL(63, 32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \

	 GENMASK_ULL(20, 10) | GENMASK_ULL(5, 5))

	 GENMASK_ULL(20, 13) | GENMASK_ULL(11, 10) | GENMASK_ULL(5, 5))

#define SPSR_EL1_AARCH32_RES0_BITS \

	(GENMASK_ULL(63,32) | GENMASK_ULL(23, 22) | GENMASK_ULL(20,20))

	(GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20))



static int valid_compat_regs(struct user_pt_regs *regs)

{

CRA Git | Maintained and supported by SUSTech CRA and CCSE