OMAP3: PRCM interrupt: only check and clear enabled PRCM IRQs (d6290a3e) · Commits · 戴 / test

While handling PRCM IRQs, mask out interrupts that are not enabled in PRM_IRQENABLE_MPU. If these are not masked out, non-enabled interrupts are caught, a WARN() is printed due to no 'handler' and the events are cleared. In addition to being noisy, this can also interfere with independent polling of this register by SR/VP code. This was noticed using SmartReflex transitions which cause the VPx_* interrupts to be handled since they are set in PRM_IRQSTATUS_MPU even but not enabled in PRM_IRQENABLE_MPU. Acked-by:

Mike Turquette <mturquette@ti.com> Signed-off-by:

Kevin Hilman <khilman@deeprootsystems.com>

arch/arm/mach-omap2/pm34xx.c

+12 −5

Original line number	Diff line number	Diff line
		@@ -267,13 +267,16 @@ static int _prcm_int_handle_wakeup(void)
		*/
		static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
		{
		u32 irqstatus_mpu;
		u32 irqenable_mpu, irqstatus_mpu;
		int c = 0;

		do {
		irqenable_mpu = prm_read_mod_reg(OCP_MOD,
		OMAP3_PRM_IRQENABLE_MPU_OFFSET);
		irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
		OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
		irqstatus_mpu &= irqenable_mpu;

		do {
		if (irqstatus_mpu & (OMAP3430_WKUP_ST \| OMAP3430_IO_ST)) {
		c = _prcm_int_handle_wakeup();

		@@ -292,7 +295,11 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
		prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
		OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

		} while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
		irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
		OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
		irqstatus_mpu &= irqenable_mpu;

		} while (irqstatus_mpu);

		return IRQ_HANDLED;
		}

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