Commit d59fca07 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

clk: rockchip: add watchdog pclk on rk3328 



The watchdog pclk is controlled from the secure GRF but we still
want to mention it explicitly to not use arbitary parent clocks
in the devicetree wdt node, so add a SGRF_GATE for it.

Suggested-by: default avatarLeonidas P. Papadakos <papadakospan@gmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 92de4cec

drivers/clk/rockchip/clk-rk3328.c

+3 −0
Original line number Diff line number Diff line
@@ -800,6 +800,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),

	GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),



	/* Watchdog pclk is controlled from the secure GRF */

	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),



	GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),

	GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),

	GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),

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