irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains

#define APB_INT_FINALSTATUS_H	0x34

#define APB_INT_BASE_OFFSET	0x04

static void dw_apb_ictl_handler(struct irq_desc *desc)

static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)

{

	struct irq_domain *d = irq_desc_get_handler_data(desc);

	struct irq_chip *chip = irq_desc_get_chip(desc);

			u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);

			generic_handle_irq(virq);

			stat &= ~(1 << hwirq);

			stat &= ~BIT(hwirq);

		}

	}

static int __init dw_apb_ictl_init(struct device_node *np,

				   struct device_node *parent)

{

	const struct irq_domain_ops *domain_ops;

	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;

	struct resource r;

	struct irq_domain *domain;

	struct irq_chip_generic *gc;

	void __iomem *iobase;

	int ret, nrirqs, irq, i;

	int ret, nrirqs, parent_irq, i;

	u32 reg;

	domain_ops = &irq_generic_chip_ops;

	/* Map the parent interrupt for the chained handler */

	irq = irq_of_parse_and_map(np, 0);

	if (irq <= 0) {

	parent_irq = irq_of_parse_and_map(np, 0);

	if (parent_irq <= 0) {

		pr_err("%pOF: unable to parse irq\n", np);

		return -EINVAL;

	}

	else

		nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));

	domain = irq_domain_add_linear(np, nrirqs,

				       &irq_generic_chip_ops, NULL);

	domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL);

	if (!domain) {

		pr_err("%pOF: unable to add irq domain\n", np);

		ret = -ENOMEM;

		gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;

	}

	irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain);

	irq_set_chained_handler_and_data(parent_irq,

				dw_apb_ictl_handle_irq_cascaded, domain);

	return 0;