Commit d590b2d4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A few driver fixes for tegra, rockchip, and st SoCs and a two-liner in
  the framework to avoid oops when get_parent ops return out of range
  values on tegra platforms"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
  clk: check for invalid parent index of orphans in __clk_init()
  clk: tegra: dfll: Properly protect OPP list
  clk: rockchip: add critical clock for rk3368
parents e6827baf d34e210e

drivers/clk/clk.c

+2 −1
Original line number Diff line number Diff line
@@ -2437,7 +2437,8 @@ static int __clk_init(struct device *dev, struct clk *clk_user) 
	hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {

		if (orphan->num_parents && orphan->ops->get_parent) {

			i = orphan->ops->get_parent(orphan->hw);

			if (!strcmp(core->name, orphan->parent_names[i]))

			if (i >= 0 && i < orphan->num_parents &&

			    !strcmp(core->name, orphan->parent_names[i]))

				clk_core_reparent(orphan, core);

			continue;

		}

drivers/clk/rockchip/clk-rk3368.c

+6 −0
Original line number Diff line number Diff line
@@ -818,6 +818,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 
	GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),

};



static const char *const rk3368_critical_clocks[] __initconst = {

	"pclk_pd_pmu",

};



static void __init rk3368_clk_init(struct device_node *np)

{

	void __iomem *reg_base;
@@ -862,6 +866,8 @@ static void __init rk3368_clk_init(struct device_node *np) 
				   RK3368_GRF_SOC_STATUS0);

	rockchip_clk_register_branches(rk3368_clk_branches,

				  ARRAY_SIZE(rk3368_clk_branches));

	rockchip_clk_protect_critical(rk3368_critical_clocks,

				      ARRAY_SIZE(rk3368_critical_clocks));



	rockchip_clk_register_armclk(ARMCLKB, "armclkb",

			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),

drivers/clk/st/clkgen-fsyn.c

+4 −4
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = { 
	.get_rate	= clk_fs660c32_dig_get_rate,

};



static const struct clkgen_quadfs_data st_fs660c32_C_407 = {

static const struct clkgen_quadfs_data st_fs660c32_C = {

	.nrst_present = true,

	.nrst	= { CLKGEN_FIELD(0x2f0, 0x1, 0),

		    CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = { 
	.get_rate	= clk_fs660c32_dig_get_rate,

};



static const struct clkgen_quadfs_data st_fs660c32_D_407 = {

static const struct clkgen_quadfs_data st_fs660c32_D = {

	.nrst_present = true,

	.nrst	= { CLKGEN_FIELD(0x2a0, 0x1, 0),

		    CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = { 
	},

	{

		.compatible = "st,stih407-quadfs660-C",

		.data = &st_fs660c32_C_407

		.data = &st_fs660c32_C

	},

	{

		.compatible = "st,stih407-quadfs660-D",

		.data = &st_fs660c32_D_407

		.data = &st_fs660c32_D

	},

	{}

};

drivers/clk/st/clkgen-pll.c

+6 −6
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = { 
	.ops		= &stm_pll3200c32_ops,

};



static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {

static const struct clkgen_pll_data st_pll3200c32_cx_0 = {

	/* 407 C0 PLL0 */

	.pdn_status	= CLKGEN_FIELD(0x2a0,	0x1,			8),

	.locked_status	= CLKGEN_FIELD(0x2a0,	0x1,			24),
@@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { 
	.ops		= &stm_pll3200c32_ops,

};



static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {

static const struct clkgen_pll_data st_pll3200c32_cx_1 = {

	/* 407 C0 PLL1 */

	.pdn_status	= CLKGEN_FIELD(0x2c8,	0x1,			8),

	.locked_status	= CLKGEN_FIELD(0x2c8,	0x1,			24),
@@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = { 
		.data = &st_pll3200c32_407_a0,

	},

	{

		.compatible = "st,stih407-plls-c32-c0_0",

		.data = &st_pll3200c32_407_c0_0,

		.compatible = "st,plls-c32-cx_0",

		.data = &st_pll3200c32_cx_0,

	},

	{

		.compatible = "st,stih407-plls-c32-c0_1",

		.data = &st_pll3200c32_407_c0_1,

		.compatible = "st,plls-c32-cx_1",

		.data = &st_pll3200c32_cx_1,

	},

	{

		.compatible = "st,stih407-plls-c32-a9",

drivers/clk/tegra/clk-dfll.c

+7 −1
Original line number Diff line number Diff line
@@ -682,11 +682,17 @@ static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) 
	struct dev_pm_opp *opp;

	int i, uv;



	rcu_read_lock();



	opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);

	if (IS_ERR(opp))

	if (IS_ERR(opp)) {

		rcu_read_unlock();

		return PTR_ERR(opp);

	}

	uv = dev_pm_opp_get_voltage(opp);



	rcu_read_unlock();



	for (i = 0; i < td->i2c_lut_size; i++) {

		if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv)

			return i;

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