Commit d58fe3cf authored by Tianci.Yin's avatar Tianci.Yin Committed by Alex Deucher
Browse files

drm/amdgpu: add interface amdgpu_gfx_init_spm_golden for Navi1x 



On Navi1x, the SPM golden settings are lost after GFXOFF
enter/exit, so reconfiguration is needed. Make the
configuration code as an interface for future use.

Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarTianci.Yin <tianci.yin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 66459e1d

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+2 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ struct amdgpu_gfx_funcs { 
	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);

	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);

	void (*reset_ras_error_count) (struct amdgpu_device *adev);

	void (*init_spm_golden)(struct amdgpu_device *adev);

};



struct sq_work {
@@ -324,6 +325,7 @@ struct amdgpu_gfx { 
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))

#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))



/**

 * amdgpu_gfx_create_bitmask - create a bitmask

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+25 −9
Original line number Diff line number Diff line
@@ -3307,6 +3307,29 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 
	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;

}



static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_NAVI10:

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_0_nv10,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));

		break;

	case CHIP_NAVI14:

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_1_nv14,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));

		break;

	case CHIP_NAVI12:

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_1_2_nv12,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));

		break;

	default:

		break;

	}

}



static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {
@@ -3317,9 +3340,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
		soc15_program_register_sequence(adev,

						golden_settings_gc_10_0_nv10,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_0_nv10,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));

		break;

	case CHIP_NAVI14:

		soc15_program_register_sequence(adev,
@@ -3328,9 +3348,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
		soc15_program_register_sequence(adev,

						golden_settings_gc_10_1_nv14,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_1_nv14,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));

		break;

	case CHIP_NAVI12:

		soc15_program_register_sequence(adev,
@@ -3339,9 +3356,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
		soc15_program_register_sequence(adev,

						golden_settings_gc_10_1_2_nv12,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));

		soc15_program_register_sequence(adev,

						golden_settings_gc_rlc_spm_10_1_2_nv12,

						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));

		break;

	case CHIP_SIENNA_CICHLID:

		soc15_program_register_sequence(adev,
@@ -3360,6 +3374,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
	default:

		break;

	}

	gfx_v10_0_init_spm_golden_registers(adev);

}



static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
@@ -4149,6 +4164,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 
	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,

	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,

	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,

	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,

};



static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)

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