ARCv2: clocksource: Rename GRTC -> GFRC ... (d584f0fb) · Commits · 戴 / test

arch/arc/Kconfig

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -413,7 +413,7 @@ config ARC_HAS_RTC
	default n		default n
	depends on !SMP		depends on !SMP

	config ARC_HAS_GRTC		config ARC_HAS_GFRC
	bool "SMP synchronized 64-bit cycle counter"		bool "SMP synchronized 64-bit cycle counter"
	default y		default y
	depends on SMP		depends on SMP

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y
	CONFIG_AXS103=y		CONFIG_AXS103=y
	CONFIG_ISA_ARCV2=y		CONFIG_ISA_ARCV2=y
	CONFIG_SMP=y		CONFIG_SMP=y
	# CONFIG_ARC_HAS_GRTC is not set		# CONFIG_ARC_HAS_GFRC is not set
	CONFIG_ARC_UBOOT_SUPPORT=y		CONFIG_ARC_UBOOT_SUPPORT=y
	CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"		CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
	CONFIG_PREEMPT=y		CONFIG_PREEMPT=y

+2 −2

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -96,13 +96,13 @@ static void mcip_probe_n_setup(void)
	#ifdef CONFIG_CPU_BIG_ENDIAN		#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad3:8,		unsigned int pad3:8,
	idu:1, llm:1, num_cores:6,		idu:1, llm:1, num_cores:6,
	iocoh:1, grtc:1, dbg:1, pad2:1,		iocoh:1, gfrc:1, dbg:1, pad2:1,
	msg:1, sem:1, ipi:1, pad:1,		msg:1, sem:1, ipi:1, pad:1,
	ver:8;		ver:8;
	#else		#else
	unsigned int ver:8,		unsigned int ver:8,
	pad:1, ipi:1, sem:1, msg:1,		pad:1, ipi:1, sem:1, msg:1,
	pad2:1, dbg:1, grtc:1, iocoh:1,		pad2:1, dbg:1, gfrc:1, iocoh:1,
	num_cores:6, llm:1, idu:1,		num_cores:6, llm:1, idu:1,
	pad3:8;		pad3:8;
	#endif		#endif
	@@ -116,7 +116,7 @@ static void mcip_probe_n_setup(void)
	IS_AVAIL1(mp.ipi, "IPI "),		IS_AVAIL1(mp.ipi, "IPI "),
	IS_AVAIL1(mp.idu, "IDU "),		IS_AVAIL1(mp.idu, "IDU "),
	IS_AVAIL1(mp.dbg, "DEBUG "),		IS_AVAIL1(mp.dbg, "DEBUG "),
	IS_AVAIL1(mp.grtc, "GRTC"));		IS_AVAIL1(mp.gfrc, "GFRC"));

	idu_detected = mp.idu;		idu_detected = mp.idu;

	@@ -125,8 +125,8 @@ static void mcip_probe_n_setup(void)
	__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);		__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
	}		}

	if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)		if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
	panic("kernel trying to use non-existent GRTC\n");		panic("kernel trying to use non-existent GFRC\n");
	}		}

	struct plat_smp_ops plat_smp_ops = {		struct plat_smp_ops plat_smp_ops = {

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -62,7 +62,7 @@

	/******** Clock Source Device *******/		/******** Clock Source Device *******/

	#ifdef CONFIG_ARC_HAS_GRTC		#ifdef CONFIG_ARC_HAS_GFRC

	static int arc_counter_setup(void)		static int arc_counter_setup(void)
	{		{
	@@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs)

	local_irq_save(flags);		local_irq_save(flags);

	__mcip_cmd(CMD_GRTC_READ_LO, 0);		__mcip_cmd(CMD_GFRC_READ_LO, 0);
	stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);		stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);

	__mcip_cmd(CMD_GRTC_READ_HI, 0);		__mcip_cmd(CMD_GFRC_READ_HI, 0);
	stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);		stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);

	local_irq_restore(flags);		local_irq_restore(flags);
	@@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs)
	}		}

	static struct clocksource arc_counter = {		static struct clocksource arc_counter = {
	.name = "ARConnect GRTC",		.name = "ARConnect GFRC",
	.rating = 400,		.rating = 400,
	.read = arc_counter_read,		.read = arc_counter_read,
	.mask = CLOCKSOURCE_MASK(64),		.mask = CLOCKSOURCE_MASK(64),