iwlagn: move PCI power related functions to the PCI layer (d57fa99d) · Commits · 戴 / test

drivers/net/wireless/iwlwifi/iwl-agn-hw.h

+0 −7

Original line number	Diff line number	Diff line
		@@ -81,13 +81,6 @@
		/* RSSI to dBm */
		#define IWLAGN_RSSI_OFFSET 44

		/* PCI registers */
		#define PCI_CFG_RETRY_TIMEOUT 0x041

		/* PCI register values */
		#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
		#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02

		#define IWLAGN_DEFAULT_TX_RETRY 15

		/* Limit range of txpower output target to be between these values */

drivers/net/wireless/iwlwifi/iwl-core.c

+1 −23

Original line number	Diff line number	Diff line
		@@ -997,8 +997,6 @@ void iwl_apm_stop(struct iwl_priv *priv)
		int iwl_apm_init(struct iwl_priv *priv)
		{
		int ret = 0;
		u16 lctl;

		IWL_DEBUG_INFO(priv, "Init card's basic functions\n");

		/*
		@@ -1027,27 +1025,7 @@ int iwl_apm_init(struct iwl_priv *priv)
		iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
		CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);

		/*
		* HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
		* Check if BIOS (or OS) enabled L1-ASPM on this device.
		* If so (likely), disable L0S, so device moves directly L0->L1;
		* costs negligible amount of power savings.
		* If not (unlikely), enable L0S, so there is at least some
		* power savings, even without L1.
		*/
		lctl = iwl_pcie_link_ctl(priv);
		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
		PCI_CFG_LINK_CTRL_VAL_L1_EN) {
		/* L1-ASPM enabled; disable(!) L0S */
		iwl_set_bit(priv, CSR_GIO_REG,
		CSR_GIO_REG_VAL_L0S_ENABLED);
		IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
		} else {
		/* L1-ASPM disabled; enable(!) L0S */
		iwl_clear_bit(priv, CSR_GIO_REG,
		CSR_GIO_REG_VAL_L0S_ENABLED);
		IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
		}
		priv->bus.ops->apm_config(&priv->bus);

		/* Configure analog phase-lock-loop before activating to D0A */
		if (priv->cfg->base_params->pll_cfg_val)

drivers/net/wireless/iwlwifi/iwl-core.h

+0 −14

Original line number	Diff line number	Diff line
		@@ -470,20 +470,6 @@ int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,

		int iwl_enqueue_hcmd(struct iwl_priv priv, struct iwl_host_cmd cmd);


		/*****************************************************
		* PCI *
		*****************************************************/

		static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
		{
		int pos;
		u16 pci_lnk_ctl;
		pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
		pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
		return pci_lnk_ctl;
		}

		void iwl_bg_watchdog(unsigned long data);
		u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval);
		__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,

drivers/net/wireless/iwlwifi/iwl-dev.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -1193,6 +1193,9 @@ struct iwl_bus;

		/**
		* struct iwl_bus_ops - bus specific operations

		* @get_pm_support: must returns true if the bus can go to sleep
		* @apm_config: will be called during the config of the APM configuration
		* @set_drv_data: set the priv pointer to the bus layer
		* @get_dev: returns the device struct
		* @write8: write a byte to register at offset ofs
		@@ -1200,6 +1203,8 @@ struct iwl_bus;
		* @wread32: read a dword at register at offset ofs
		*/
		struct iwl_bus_ops {
		bool (get_pm_support)(struct iwl_bus bus);
		void (apm_config)(struct iwl_bus bus);
		void (set_drv_data)(struct iwl_bus bus, void *priv);
		struct device (get_dev)(const struct iwl_bus *bus);
		void (write8)(struct iwl_bus bus, u32 ofs, u8 val);

drivers/net/wireless/iwlwifi/iwl-pci.c

+52 −0

Original line number	Diff line number	Diff line
		@@ -66,6 +66,12 @@
		#include "iwl-pci.h"
		#include "iwl-agn.h"
		#include "iwl-core.h"
		#include "iwl-io.h"

		/* PCI registers */
		#define PCI_CFG_RETRY_TIMEOUT 0x041
		#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
		#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02

		struct iwl_pci_bus {
		/* basic pci-network driver stuff */
		@@ -81,6 +87,50 @@ struct iwl_pci_bus {
		#define IWL_BUS_GET_PCI_DEV(_iwl_bus) \
		((IWL_BUS_GET_PCI_BUS(_iwl_bus))->pci_dev)

		static u16 iwl_pciexp_link_ctrl(struct iwl_bus *bus)
		{
		int pos;
		u16 pci_lnk_ctl;
		struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);

		pos = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
		pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
		return pci_lnk_ctl;
		}

		static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
		{
		u16 lctl = iwl_pciexp_link_ctrl(bus);

		return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
		}

		static void iwl_pci_apm_config(struct iwl_bus *bus)
		{
		/*
		* HW bug W/A for instability in PCIe bus L0S->L1 transition.
		* Check if BIOS (or OS) enabled L1-ASPM on this device.
		* If so (likely), disable L0S, so device moves directly L0->L1;
		* costs negligible amount of power savings.
		* If not (unlikely), enable L0S, so there is at least some
		* power savings, even without L1.
		*/
		u16 lctl = iwl_pciexp_link_ctrl(bus);

		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
		PCI_CFG_LINK_CTRL_VAL_L1_EN) {
		/* L1-ASPM enabled; disable(!) L0S */
		iwl_set_bit(bus->priv, CSR_GIO_REG,
		CSR_GIO_REG_VAL_L0S_ENABLED);
		IWL_DEBUG_POWER(bus->priv, "L1 Enabled; Disabling L0S\n");
		} else {
		/* L1-ASPM disabled; enable(!) L0S */
		iwl_clear_bit(bus->priv, CSR_GIO_REG,
		CSR_GIO_REG_VAL_L0S_ENABLED);
		IWL_DEBUG_POWER(bus->priv, "L1 Disabled; Enabling L0S\n");
		}
		}

		static void iwl_pci_set_drv_data(struct iwl_bus bus, void drv_priv)
		{
		pci_set_drvdata(IWL_BUS_GET_PCI_DEV(bus), drv_priv);
		@@ -108,6 +158,8 @@ static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
		}

		static struct iwl_bus_ops pci_ops = {
		.get_pm_support = iwl_pci_is_pm_supported,
		.apm_config = iwl_pci_apm_config,
		.set_drv_data = iwl_pci_set_drv_data,
		.get_dev = iwl_pci_get_dev,
		.write8 = iwl_pci_write8,

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