Commit d56eaa7c authored Sep 06, 2019 by Joshua Aberback Committed by Alex Deucher Oct 10, 2019

drm/amd/display: Add missing shifts and masks for dpp registers on dcn2



[Why]
The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is
called from dpp2_cnv_setup, but the shifts and masks for the fields of that
register are not initialized for dcn2. This causes all reads of that register
to return 0.

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent deb79818

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -581,11 +581,13 @@ static const struct dcn2_dpp_registers tf_regs[] = {
		};

		static const struct dcn2_dpp_shift tf_shift = {
		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
		TF_DEBUG_REG_LIST_SH_DCN10
		};

		static const struct dcn2_dpp_mask tf_mask = {
		TF_REG_LIST_SH_MASK_DCN20(_MASK)
		TF_REG_LIST_SH_MASK_DCN20(_MASK),
		TF_DEBUG_REG_LIST_MASK_DCN10
		};

		#define dwbc_regs_dcn2(id)\

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